Processors having virtually clustered cores and cache slices

A method comprising:

• executing instructions and processing data with a plurality of cores, the plurality of cores comprising symmetric multi-threaded cores;
• storing the instructions and the data in a cache subsystem, the cache subsystem comprising a plurality of first level caches and at least one higher level distributed cache comprising a plurality of distributed cache portions that are physically distributed across a die, each first level cache integral to one of the plurality of cores and each distributed cache portion accessible to each of the plurality of cores;
• sharing the plurality of distributed cache portions among the plurality of cores;
• providing coherent, non-uniform access to the plurality of distributed cache portions by the plurality of cores;
• enabling a first frequency to be set for a first cluster of the plurality of cores which are physically proximate to one another and a second frequency to be set for a second cluster of the plurality of cores which are physically proximate to one another, wherein an average distance between cores in the first cluster is less than an average distance between the plurality of cores;
• selectively gating power to the first cluster of the plurality of cores and distributed cache portions that correspond to the first cluster and/or the second cluster of the plurality of cores and distributed cache portions that correspond to the second cluster;
• controlling access by the symmetric multi-threaded cores to a first system memory with a first integrated memory controller;
• and
• controlling access by the symmetric multi-threaded cores to a second system memory with a second integrated memory controller.

A machine comprising:

• a processor comprising:
• a plurality of cores, the plurality of cores comprising symmetric multi-threaded cores;
• a cache subsystem, the cache subsystem comprising a plurality of first level caches and at least one higher level distributed cache comprising a plurality of distributed cache portions that are physically distributed across a die and shared by the plurality of cores, each first level cache integral to one of the plurality of cores and each distributed cache portion accessible to each of the plurality of cores;
• and
• cache management circuitry configured to provide coherent, non-uniform access to the plurality of distributed cache portions by the plurality of cores;
• an article of manufacture comprising a machine-readable storage medium storing a plurality of instructions, the plurality of instructions, when performed by the machine, causing the machine to perform operations comprising:
• enable a first frequency of operation for a first cluster of the plurality of cores which are physically proximate to one another and a second frequency of operation for a second cluster of the plurality of cores which are physically proximate to one another, wherein an average distance between cores in the first cluster is less than an average distance between the plurality of cores;
• and
• selectively gate power to the first cluster of the plurality of cores and distributed cache portions that correspond to the first cluster and/or the second cluster of the plurality of cores and distributed cache portions that correspond to the second cluster;
• a first integrated memory controller coupled with the symmetric multi-threaded cores;
• and
• a second integrated memory controller coupled with the symmetric multi-threaded cores.