Selectively updating a coherence state in response to a storage update

A processing unit for a data processing system, said processing unit comprising:

• a processor core;
• a cache memory coupled to the processor core, wherein the cache memory stores a cache line in association with a coherence state field set to a first modified coherence state among a plurality of modified coherence states and implements a default first coherence state update policy in which the cache memory is biased to retain write authority for the cache line, wherein the cache memory is configured to, responsive to a store request of the processor core:
• update data of the cache line utilizing store data of the store request;
• in response to the store request indicating a change from the default first coherence state update policy, update the coherence state field from the first modified coherence state to a second modified coherence state among the plurality of modified coherence states in which the cache memory is biased to transfer write authority for the cache line;
• and
• in response to the store request not indicating a change from the default first coherence state policy, refrain from updating the coherence state field from the first modified coherence state.

A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• A processing unit for a data processing system, said processing unit comprising:
• a processor core;
• a cache memory coupled to the processor core, wherein the cache memory stores a cache line in association with a coherence state field set to a first modified coherence state among a plurality of modified coherence states and implements a default first coherence state update policy in which the cache memory is biased to retain write authority for the cache line, wherein the cache memory is configured to, responsive to a store request of the processor core:
• update data of the cache line utilizing store data of the store request;
• in response to the store request indicating a change from the default first coherence state update policy, update the coherence state field from the first modified coherence state to a second modified coherence state among the plurality of modified coherence states in which the cache memory is biased to transfer write authority for the cache line;
• and
• in response to the store request not indicating a change from the default first coherence state policy, refrain from updating the coherence state field from the first modified coherence state.