Scan synchronous-write-through testing architectures for a memory device

A memory device, comprising:

• a memory array, row selection circuitry, column selection circuitry, and a sense amplifier/write driver configured to be disabled in a testing mode of operation;
• and
• an output latch configured to:
• receive an input sequence of data in the testing mode of operation in accordance with a memory clocking signal, and
• deliver the output sequence of data in accordance with the memory clocking signal in the testing mode of operation,
• wherein the output latch is configured to:
• receive the input sequence upon a rising edge of the memory clocking signal, and
• deliver the output sequence of data upon a falling edge of the memory clocking signal.

A memory storage device, comprising:

• first latching circuitry configured to provide a serial sequence of data in a first mode of operation or in a second mode of operation or a parallel sequence of data in a third mode of operation in accordance with a memory clocking signal;
• a memory device, having first internal circuitry and second internal circuitry, configured to:
• pass the serial sequence of data in the first mode of operation and the parallel sequence of data in the third mode of operation through the first internal circuitry to provide a first sequence of output data, and
• disable the second internal circuitry of the memory device in the first mode of operation and the third mode of operation;
• latching circuitry configured to pass through, bypassing the memory device, the serial sequence of data in the second mode of operation to provide a second sequence of output data in accordance with the memory clocking signal;
• and
• multiplexing circuitry configured to provide the first sequence of output data in the first mode of operation and in the third mode of operation or the second sequence of output data in the second mode of operation.

A memory device, comprising:

• a memory array, row selection circuitry, and column selection circuitry configured to be disabled in a testing mode of operation;
• and
• an output latch, a write driver, and a sense amplifier, at least one of the output latch, the write driver, and the sense amplifier being configured to:
• receive an input sequence of data in the testing mode of operation in accordance with a memory clocking signal,
• operate on the input sequence of data to provide an output sequence of data in the testing mode of operation, and
• deliver the output sequence of data in accordance with the memory clocking signal in the testing mode of operation.