Program verify adaptation for flash memory

A solid state drive for facilitating adaption of program verify offsets for a plurality of memory cells, the solid state drive comprising:

• a plurality of memory devices comprising one or more dies, wherein each of the one or more dies comprises blocks, wherein each of the blocks comprises wordlines, wherein each of the wordlines comprises memory cells;
• and
• a controller configured to:
• program the plurality of memory cells within the one or more dies into N states, wherein each of the N states of the plurality of memory cells is associated with a program verify voltage;
• perform an adjustment iteration on the one or more dies, wherein performing the adjustment iteration includes incrementing or decrementing the program verify offsets in an iterative manner to distribute errors across pages stored in the plurality of memory devices, wherein performing the adjustment iteration facilitates improvement of bit error correction and the solid state drive's reliability over not performing the adjustment iteration, and wherein performing the adjustment iteration comprises:
• accessing error counts for respective N states of the plurality of memory cells in a memory device of the plurality of memory devices, wherein the error counts are for errors between the respective N states and adjacent lower states;
• applying a weighting to the error counts, wherein the weighting is based on a binary data coding for the N states;
• determining a state Smin of the N states having a minimum error count Emin from the error counts;
• determining a state Smax of the N states having a maximum error count Emax from the error counts;
• determining a difference between the Emax and the Emin satisfies an error count threshold;
• and
• adjusting, by a predefined value, a respective program verify offset of a lowest state from Smin and Smax, and of each state between Smin and Smax in the N states,
• wherein the predefined value is a voltage increment recognizable by a digital-to-analog converter circuit for performing reads on one or more memory cells in the memory device of the plurality of memory devices,
• wherein the adjusting is a decrement when Smin is less than Smax, and
• wherein the adjusting is an increment when Smin is greater than Smax;
• repeat the performing of the adjustment iteration until the difference between the Emax and the Emin does not satisfy the error count threshold, wherein a minimum number of read operations on data programmed with the adjusted program verify offsets is met after each repeating;
• store the adjusted program verify offsets into registers;
• and
• program at least some of the wordlines using the adjusted program verify offsets.

A non-transitory machine-readable medium including machine-executable instructions thereon that, when executed by a processor, perform a method for adapting a plurality of program verify offsets for a memory of a solid state drive (SSD), wherein the method comprises:

• programming the memory by the processor, wherein the processor is coupled to the memory, wherein the memory comprises one or more dies, wherein each of the one or more dies comprises blocks, wherein each of the blocks comprises wordlines, wherein each of the wordlines comprises memory cells, wherein the programming programs a plurality of memory cells within the one or more dies into N states, wherein each of the N states of the plurality of memory cells is associated with a program verify voltage;
• determining, by the processor, an adaptation is due for adjusting program verify offsets for the N states of the plurality of memory cells, wherein the determining is by a program/erase (P/E) cycle count for the plurality of memory cells reaching a periodic threshold value;
• and
• performing, by the processor, an adjustment iteration on the one or more dies, wherein performing the adjustment iteration includes incrementing or decrementing the program verify offsets in an iterative manner to distribute errors across pages stored in the memory, wherein performing the adjustment iteration improves bit error correction and the SSD's reliability over not performing the adjustment iteration, and wherein performing the adjustment iteration comprises:
• accessing, by the processor, error counts for the respective N states of the plurality of memory cells within the one or more dies, wherein the error counts are for errors between the respective N states and adjacent lower states;
• applying, by the processor, a weighting to the error counts, wherein the weighting is based on a binary data coding for the N states;
• determining, by the processor, a state Smin of the N states having a minimum error count Emin from the error counts;
• determining, by the processor, a state Smax of the N states having a maximum error count Emax from the error counts;
• determining, by the processor, a difference between the Emax and the Emin satisfies an error count threshold;
• and
• adjusting using the processor, by a predefined value, a respective program verify offset of a lowest state from Smin and Smax, and of each state between Smin and Smax in the N states,
• wherein the predefined value is a voltage increment recognizable by a digital-to-analog converter circuit for performing reads on one or more memory cells within the one or more dies,
• wherein the adjusting is a decrement when Smin is less than Smax, and
• wherein the adjusting is an increment when Smin is greater than Smax;
• storing, by the processor, the adjusted program verify offsets into registers;
• and
• programming, by the processor, at least some of the wordlines using the adjusted program verify offsets.

A system for facilitating adaption of program verify offsets for a memory, the system comprising:

• means for programming the memory, wherein the memory comprises one or more dies, wherein each of the one or more dies comprises blocks, wherein each of the blocks comprises wordlines, wherein each of the wordlines comprises memory cells, wherein the programming programs a plurality of memory cells within the one or more dies into N states, wherein each of the N states of the plurality of memory cells is associated with a program verify voltage;
• means for performing an adjustment iteration, wherein the means for performing the adjustment iteration includes means for incrementing or decrementing the program verify offsets in an iterative manner to distribute errors across pages stored in the memory, wherein the means for performing the adjustment iteration facilitates improvement of bit error correction and the system's reliability over not performing the adjustment iteration, and wherein the means for performing the adjustment iteration comprises:
• means for accessing error counts for the respective N states of the plurality of memory cells within the one or more dies, wherein the error counts are for errors between the respective N states and adjacent lower states;
• means for applying a weighting to the error counts, wherein the weighting is based on a binary data coding for the N states;
• means for determining a state Smin of the N states having a minimum error count Emin from the error counts;
• means for determining a state Smax of the N states having a maximum error count Emax from the error counts;
• means for determining a difference between the Emax and the Emin satisfies an error count threshold;
• and
• means for adjusting, by a predefined value, a respective program verify offset of a lowest state from Smin and Smax, and of each state between Smin and Smax in the N states,
• wherein the predefined value is a voltage increment recognizable by a digital-to-analog converter circuit for performing reads on one or more memory cells within the one or more dies,
• wherein the adjusting is a decrement when Smin is less than Smax, and
• wherein the adjusting is an increment when Smin is greater than Smax;
• means for repeating the performing of the adjustment iteration until the difference between the Emax and the Emin does not satisfy the error count threshold, wherein a threshold number of read operations on data programmed with the adjusted program verify offsets is met after each repeating;
• means for storing the adjusted program verify offsets into registers;
• and
• means for programming at least some of the wordlines using the adjusted program verify offsets.