Wide vector execution in single thread mode for an out-of-order processor

A system for wide vector execution for an out-of-order processor, the system comprising:

• a memory having computer readable instructions;
• and
• the out-of-order processor for executing the computer readable instructions, the computer readable instructions controlling the out-of-order processor to perform operations comprising:
• partitioning a vector register file into a plurality of register files, each of the plurality of register files being associated with a vector execution unit, the vector execution units forming a wide vector execution unit, wherein each of the plurality of register files has three read wires and four write wires connected to its associated vector execution unit;
• receiving a wide vector instruction at a vector scalar register;
• determining whether the out-of-order processor is operating a single thread mode or a multi-thread mode;
• responsive to determining that the out-of-order processor is operating in the single thread mode, processing the wide vector instruction in the wide vector execution unit;
• and
• responsive to determining that the out-of-order processor is operating in the multi-thread mode, preventing processing the wide vector instruction.