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US 10,705,845 B2Granted
Instructions and logic for vector bit field compression and expansion
AssigneeIntel IP Corporation
InventorsElmoustapha Ould-Ahmed-Vall, Thomas Willhalm, Robert Valentine
Life of this patent
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Abstract
A processor includes a core to execute an instruction for conversion between an element array and a packed bit array. The core includes logic to identify one or more bit-field lengths to be used by the packed bit array, identify a width of elements of the element array, and simultaneously for elements of the element array and for bit-fields of the packed bit array, convert between the element array and the packed bit array based upon the bit-field length and the width of elements of the element array.
Claims25
A processor, comprising:
- decode circuitry to decode an instruction, wherein the instruction comprises:
- a plurality of fields to identify a destination operand, a first source operand, and a second source operand;
- and
- an opcode to indicate to execution circuitry to compress a plurality of data elements in the first source operand into a plurality of compressed data elements of one or more corresponding sizes indicated by the second source operand and store the plurality of compressed data elements in the destination operand;
- and
- the execution circuitry to execute the decoded instruction, wherein the execution circuitry comprises circuitry to:
- compress the plurality of data elements in the first source operand into the plurality of compressed data elements of the one or more corresponding sizes indicated by the second source operand;
- and
- store the plurality of compressed data elements in the destination operand.
6 more elements
A system, comprising:
- a memory to store a plurality of instructions, wherein the plurality of instructions comprises a vector compression instruction;
- and
- a processor to execute the vector compression instruction, wherein the processor comprises circuitry to:
- receive the vector compression instruction from the memory;
- decode the vector compression instruction, wherein the vector compression instruction comprises:
- a plurality of fields to identify a destination operand, a first source operand, and a second source operand;
- and
- an opcode to indicate to the processor to compress a plurality of data elements in the first source operand into a plurality of compressed data elements of one or more corresponding sizes indicated by the second source operand and store the plurality of compressed data elements in the destination operand;
- compress the plurality of data elements in the first source operand into the plurality of compressed data elements of the one or more corresponding sizes indicated by the second source operand;
- and
- store the plurality of compressed data elements in the destination operand.
8 more elements
At least one non-transitory machine accessible storage medium having instructions stored thereon, wherein the instructions, when executed on a machine, cause the machine to:
- receive a vector compression instruction from memory;
- decode the vector compression instruction, wherein the vector compression instruction comprises:
- a plurality of fields to identify a destination operand, a first source operand, and a second source operand;
- and
- an opcode to instruct a processing device to compress a plurality of data elements in the first source operand into a plurality of compressed data elements of one or more corresponding sizes indicated by the second source operand and store the plurality of compressed data elements in the destination operand;
- execute the vector compression instruction, wherein execution of the vector compression instruction causes the machine to:
- compress the plurality of data elements in the first source operand into the plurality of compressed data elements of the one or more corresponding sizes indicated by the second source operand;
- and
- store the plurality of compressed data elements in the destination operand.
6 more elements
A method, comprising:
- receiving a vector compression instruction from memory;
- decoding the vector compression instruction, wherein the vector compression instruction comprises:
- a plurality of fields to identify a destination operand, a first source operand, and a second source operand;
- and
- an opcode to instruct a processing device to compress a plurality of data elements in the first source operand into a plurality of compressed data elements of one or more corresponding sizes indicated by the second source operand and store the plurality of compressed data elements in the destination operand;
- executing the vector compression instruction, wherein executing the vector compression instruction comprises:
- compressing the plurality of data elements in the first source operand into the plurality of compressed data elements of the one or more corresponding sizes indicated by the second source operand;
- and
- storing the plurality of compressed data elements in the destination operand.
6 more elements
Dependencies are inferred from the claim text.