Apparatuses for integrating arithmetic with logic operations

An apparatus for integrating arithmetic with logic operations, comprising:

• a calculation device, calculating source data to generate and output first destination data;
• and
• a normalization unit, coupled to the calculation device, normalizing the first destination data to generate second destination data of a first type when receiving a signal indicating an output of first-type data, and normalizing the first destination data to generate the second destination data of a second type when receiving the signal indicating an output of second-type data;
• wherein the normalization unit comprises:
• a shifter;
• an adder;
• a comparator, coupled to the shifter and the adder, wherein the comparator, the shifter and the adder form a loop for performing a normalization of a floating-point value;
• and
• a merger, coupled to the shifter and the adder, combining a sign bit, a mantissa output from the shifter and an exponent output from the adder to generate the second destination data.