US 10,705,839 B2 · Apparatus and method for multiplying, summing, and accumulating sets of packed bytes

Abstract

A processor having a decoder to decode an instruction to generate a decoded instruction; a first source register to store a first plurality of packed signed bytes; a second source register to store a second plurality of packed signed bytes; execution circuitry to execute the decoded instruction, the execution circuitry including: multiplier circuitry to multiply each packed signed byte from the first source register with a corresponding packed signed byte from the second source register to generate temporary products, adder circuitry to add a plurality of sets of the temporary products to generate a plurality of temporary sums; negation and extension circuitry to negate and extend each of the temporary sums to doublewords sums; and accumulation circuitry to add each of the doublewords sums to a doubleword from a third source register to generate final doubleword results; and a packed data destination register to store the final doubleword results.

Claims21

Dependent claims

A processor comprising:

a decoder to decode an instruction, the instruction including an opcode, and a plurality of operands identifying a plurality of packed data source registers and a packed data destination register;
a first source register to store a first plurality of packed signed bytes;
a second source register to store a second plurality of packed signed bytes;
execution circuitry to execute the decoded instruction, the execution circuitry comprising:
multiplier circuitry to multiply each packed signed byte from the first source register with a corresponding packed signed byte from the second source register to generate a plurality of temporary products,
adder circuitry to add a plurality of sets of the temporary products to generate a plurality of temporary sums;
negation and extension circuitry to negate and extend each of the temporary sums to doublewords sums;
and
accumulation circuitry to add each of the doublewords sums to a doubleword from a third source register to generate final doubleword results;
and
a packed data destination register to store the final doubleword results in specified data element locations.

8 more elements

Dependencies are inferred from the claim text.

Apparatus and method for multiplying, summing, and accumulating sets of packed bytes

Life of this patent

Apparatus and method for multiplying, summing, and accumulating sets of packed bytes

Life of this patent

Abstract

Claims21