Multiplication operations in memory
AssigneeMicron Technology, Inc.
InventorSanjay Tiwari
Life of this patent
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Abstract
Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.
Claims20
A system, comprising:
- a processing resource configured to generate instructions;
- and
- a memory device coupled to the processing resource and comprising:
- an array of memory cells;
- a plurality of sense amplifiers coupled to the array;
- and
- a plurality of compute components coupled to the plurality of sense amplifiers;
- wherein the memory device is configured to execute the instructions to multiply, in parallel, a plurality of element pairs stored in the array by controlling the plurality of sense amplifiers and the plurality of compute components to perform logical operation processing on data without moving the data to the processing resource.
A method, comprising:
- receiving, to a memory device, an instruction to perform a plurality of multiplication operations on a respective plurality of element pairs stored in an array of the memory device;
- and
- executing the instruction on the memory device, wherein executing the instruction comprises controlling sense amplifiers and compute components of the memory device to multiply the plurality of element pairs and obtain respective results by performing a number of logical operations, in parallel, without transferring data to a processing resource from which the instruction was received;
- wherein the sense amplifiers are coupled to the array of the memory device and the compute components are coupled to the sense amplifiers.
An apparatus, comprising:
- an array of memory cells;
- sense amplifiers coupled to the array;
- and
- compute components coupled to the sense amplifiers;
- wherein the array is configured to:
- store, in a first group of memory cells coupled to a first access line, a first bit-vector comprising a plurality of first elements of a respective plurality of element pairs;
- and
- store, in a second group of memory cells coupled to a second access line, a second bit-vector comprising a plurality of second elements of the respective plurality of element pairs;
- and
- a controller configured to provide signals to the sense amplifiers and to the compute components to perform logical operation processing to multiply, in parallel, respective corresponding element pairs of the plurality of element pairs by each other;
- and
- wherein the memory device is configured to perform the multiplication and to store a results bit-vector in the array without transferring data to an external processing resource from the sense amplifiers and without transferring data to the external processing resource from the compute components.
Dependencies are inferred from the claim text.