Parallel-prefix adder and method

An adder comprising:

• a signals generation circuit configured to receive two addends and to generate, for all bit pair of same position bits in the two addends, corresponding propagation and generation signals;
• and
• a primary carry bit generation circuit configured to receive the corresponding propagation and generation signals and to generate primary carry bits, wherein the primary carry bit generation circuit comprises:
• a first section using the corresponding propagation and generation signals for each bit pair in a first sequential set of bit pairs to generate first primary carry bits at a first carry bit-to-bit pair ratio of 1:2;
• a second section using the corresponding propagation and generation signals for each bit pair in a second sequential set of bit pairs to generate second primary carry bits at a second carry bit-to-bit pair ratio of 1:4;
• and
• a third section using the corresponding propagation and generation signals for each bit pair in a third sequential set of bit pairs to generate third primary carry bits at a third carry bit-to-bit pair ratio of 1:2.

A method of forming an adder to compute a sum of two addends, the method comprising:

• determining a maximum number of bits per addend;
• noting whether the maximum number is an odd number or an even number;
• and
• forming a primary carry bit generation circuit configured to receive corresponding propagation and generation signals for all bit pairs of same position bits in the two addends and to generate primary carry bits associated with some of the bit pairs,
• wherein the primary carry bits are associated with different bit pairs depending upon whether the maximum number is an odd number or an even number, and
• wherein the forming of the primary carry bit generation circuit comprises:
• forming a first section that uses the corresponding propagation and generation signals for each bit pair in a first sequential set of bit pairs to generate first primary carry bits at a first carry bit-to-bit pair ratio;
• forming a second section that uses the corresponding propagation and generation signals for each bit pair in a second sequential set of bit pairs to generate second primary carry bits at a second carry bit-to-bit pair ratio that is less than the first carry bit-to-bit pair ratio;
• and
• forming a third section that uses the corresponding propagation and generation signals for each bit pair in a third sequential set of bit pairs to generate third primary carry bits at a third carry bit-to-bit pair ratio that is equal to the first carry bit-to-bit pair ratio.