3D cross-bar nonvolatile memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJean-Pierre Colinge, Carlos H. Diaz, Ta-Pen Guo
Life of this patent
Estimating the term…
Abstract
Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.
Claims20
A method of forming a semiconductor structure, the method comprising:
- forming a doped nanowire structure on a substrate having a plurality of transistors;
- forming a charge-trapping stack of layers directly on the doped nanowire structure;
- forming a gate electrode on the charge-trapping stack of layers;
- forming a first interconnect between the doped nanowire structure and a first transistor of the plurality of transistors;
- and
- forming a second interconnect between the gate electrode and a second transistor of the plurality of transistors.
A method of forming a semiconductor structure, the method comprising:
- forming a crystalline semiconductor structure;
- forming a gate structure directly on the crystalline semiconductor structure, wherein forming the gate structure comprises:
- depositing an oxide-nitride-oxide charge-trapping stack over the crystalline semiconductor structure;
- depositing a gate electrode layer over the oxide-nitride-oxide charge-trapping stack;
- and
- patterning the gate electrode layer;
- forming a first interconnect to electrically couple the crystalline semiconductor structure to a first terminal of a first semiconductor device;
- and
- forming a second interconnect to electrically couple the gate structure to a second terminal of a second semiconductor device.
A semiconductor structure, comprising:
- a crystalline semiconductor structure;
- a gate structure directly on the crystalline semiconductor structure, the gate structure comprising:
- a charge-trapping gate dielectric stack;
- and
- an electrically conductive gate electrode on the charge-trapping gate dielectric stack;
- a first interconnect electrically coupling the crystalline semiconductor structure to a first terminal of a first semiconductor device;
- and
- a second interconnect electrically coupling the gate structure to a second terminal of a second semiconductor device.
Dependencies are inferred from the claim text.