Power-conserving cache memory usage

A method comprising:

• operating a memory system that includes a first cache memory, a supplemental cache memory, and a main memory;
• the supplemental cache memory comprising at least one computer-readable storage medium that is physically separate from the first cache memory, the supplemental cache memory smaller and configured to store less information than the first cache memory, the supplemental cache memory configured to selectively handle cache misses or cache overflows of the first cache memory;
• determining an operational mode of the supplemental cache memory, the operational mode comprising an inactive operational mode or an active operational mode;
• responsive to the supplemental cache memory being in the inactive operational mode and the main memory being in a regular power mode,
• bypassing the supplemental cache memory for a memory request associated with a cache miss or a cache overflow of the first cache memory;
• and
• routing the memory request to the main memory;
• and
• responsive to the supplemental cache memory being in the active operational mode and the main memory being in a low-power mode,
• determining that information targeted by the memory request is stored in the supplemental cache memory;
• and
• responsive to determining that the targeted information is stored in the supplemental cache memory, providing, from the supplemental cache memory, the targeted information.

An electronic device comprising:

• one or more processors;
• and
• one or more computer-readable storage media including:
• a first cache memory at a first hierarchical level;
• a main memory at a third hierarchical level;
• a supplemental cache memory at a second hierarchical level, the supplemental cache memory communicatively coupled between the first cache memory and the main memory, the supplemental cache memory comprising at least one computer-readable storage medium that is physically separate from the first cache memory, the supplemental cache memory smaller and configured to store less information than the first cache memory, the second hierarchical level lower than the first hierarchical level, the third hierarchical level lower than the second hierarchical level;
• a register configured to hold a settable value;
• and
• instructions stored on the one or more computer-readable storage media that, responsive to execution by the one or more processors, cause to be performed operations comprising:
• causing code to execute on the one or more processors;
• and
• adjusting the settable value based on the code to selectively enable the supplemental cache memory to operate as a lower-level cache resource with respect to the first cache memory, including:
• enabling the supplemental cache memory to operate as the lower-level cache resource based on the supplemental cache memory being in an active operational mode and the main memory being in a low-power mode;
• and
• disabling the supplemental cache memory from operating as the lower-level cache resource based on the supplemental cache memory being in an inactive operational mode and the main memory being in a regular power mode.