Enabling a non-core domain to control memory bandwidth in a processor

A system comprising:

• a system memory;
• a plurality of cores coupled to the system memory;
• a first core of the plurality of cores operable at a first voltage and at a first frequency, and a second core of the plurality of cores operable at a second voltage independent of the first voltage and at a second frequency different from the first frequency;
• graphics processing circuitry coupled to the plurality of cores to perform graphics operations, the graphics processing circuitry independently operable at a third frequency different from the first frequency and the second frequency;
• and
• an interconnect to couple the graphics processing circuitry to the system memory, the interconnect operable at a fourth frequency different from at least the first and second frequencies.

An apparatus comprising:

• means for operating a first core at a first voltage and at a first frequency while concurrently operating a second core at a second voltage independent of the first voltage and at a second frequency different from the first frequency;
• means for independently operating a graphics processor at a third frequency different from the first frequency and the second frequency;
• and
• interconnect means to couple the graphics processor to a memory device, the interconnect means operable at a fourth frequency different from the first, second, and third frequencies.