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US 10,705,560 B1Granted
Signal path blanking during common mode input transitions
AssigneeAllegro MicroSystems, LLC
InventorCraig S. Petrie
Life of this patent
Estimating the term…
Abstract
A sensor includes an analog front end having a circuit element responsive to a clock signal and a clock generating circuit configured to generate the clock signal having blanking time periods during which the clock signal is held at a constant level, wherein the circuit element is not operational during the blanking time periods. The blanking time periods correspond to time periods during which transitions of a common mode input voltage to the sensor are expected to occur.
Claims18
A sensor comprising:
- an analog front end comprising a circuit element responsive to a clock signal;
- and
- a clock generating circuit configured to generate the clock signal having blanking time periods during which the clock signal is held at a constant level, wherein the circuit element is not operational during the blanking time periods.
A method comprising:
- providing a sensor with an analog front end having a circuit element responsive a clock signal;
- and
- generating the clock signal having blanking time periods during which the clock signal is held at a constant level, wherein the circuit element is not operational during the blanking time periods.
A sensor comprising:
- an analog front end comprising a circuit element responsive to a clock signal;
- and
- means for generating the clock signal having blanking time periods during which the clock signal is held at a constant level, wherein the circuit element is not operational during the blanking time periods.
Dependencies are inferred from the claim text.