US 10,705,558 B2Granted

Apparatuses and methods for avoiding glitches when switching clock sources

AssigneeQUALCOMM Incorporated

InventorsYu Huang, Nam Dang

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Abstract

Certain aspects of the present disclosure provide an input clock switching system, including: a clock source configured to output a reference clock signal; a clock generator circuit connected to the clock source and configured to output a plurality of input clock signals based on the reference clock signal; an output clock multiplexer, configured to: receive the plurality of input clock signals; receive an output clock selection signal; and output a first clock signal, wherein the first clock signal is one of the input clock signals; and a glitch suppression circuit, configured to: receive the first clock signal; receive a glitch suppression signal; output a clock output signal, wherein the clock output signal is: the first clock signal when the glitch suppression signal is in a first state; and a logic low signal when the glitch suppression signal is in a second state.

Claims11

Dependent claims

An input clock switching system, comprising:

a clock source configured to output a reference clock signal;
a clock generator circuit connected to the clock source and configured to output a plurality of input clock signals based on the reference clock signal;
a first latch, configured to:
receive a selection code;
and
receive a clock output signal;
and
output an input clock selection signal;
a clock preselection multiplexer, configured to:
receive the plurality of input clock signals;
receive the input clock selection signal;
and
output a preselected clock signal;
a second latch, configured to:
receive the input clock selection signal;
receive a glitch suppression signal;
and
output an output clock selection signal
an output clock multiplexer, configured to:
receive the plurality of input clock signals;
receive the output clock selection signal;
and
output a selected clock signal, wherein the selected clock signal is one of the plurality of input clock signals;
and
a logic gate, configured to:
receive the preselected clock signal;
receive the clock output signal;
and
output the glitch suppression signal based on the preselected clock signal and the clock output signal;
and
a glitch suppression circuit, configured to:
receive the selected clock signal from the output clock multiplexer;
receive the glitch suppression signal from the logic gate;
and
output the clock output signal, wherein the clock output signal is:
the selected clock signal when the glitch suppression signal is in a first state;
and
a logic low signal when the glitch suppression signal is in a second state.

35 more elements

A method for suppressing glitches during switches between clock input sources, comprising:

outputting a first clock signal;
receiving a signal to switch from the first clock signal to a second clock signal;
suppressing a glitch during a transition between the first clock signal and the second clock signal by:
receiving, at a first latch, a selection code;
receiving, at the first latch, a clock output signal;
outputting, from the first latch, an input clock selection signal;
receiving, at a clock preselection multiplexer, a plurality of input clock signals from a clock generator circuit;
receiving, at the clock preselection multiplexer, the input clock selection signal;
outputting, from the clock preselection multiplexer, a preselected clock signal;
receiving, at a second latch, the input clock selection signal;
receiving, at the second latch, a glitch suppression signal;
outputting, from the second latch, and output clock selection signal;
receiving, at an output clock multiplexer, the plurality of input clock signals from a clock signal generator;
receiving, at the output clock multiplexer, the output clock selection signal;
outputting, from the output clock multiplexer, a selected clock signal, wherein the selected clock signal is one of the plurality of input clock signals;
receiving, at a logic gate, the preselected clock signal;
receiving, at the logic gate, the clock output signal;
outputting, from the logic gate, the glitch suppression signal based on the preselected clock signal and the clock output signal;
receiving, at a glitch suppression circuit, the selected clock signal from the output clock multiplexer;
receiving, at the glitch suppression circuit, the glitch suppression signal from the logic gate;
outputting, from the glitch suppression circuit, the selected clock signal when the glitch suppression signal is in a first state;
outputting, from the glitch suppression circuit, a logic low signal when the glitch suppression signal is in a second state;
and
outputting the second clock signal, wherein the second clock signal is the selected clock signal.

21 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/967,344Filed 30 Apr 2018
Published: US 2019/0332136 A131 Oct 2019
Granted: 7 Jul 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
H03K 5/1252
Discriminating pulses: suppression or limitation of noise or interference
G06F 1/06
Generating or distributing clock signals or signals derived directly therefrom: clock generators producing several clock signals
H03K 19/20
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits: characterised by logic function, e.g. AND, OR, NOR, NOT…