Content addressable memory
AssigneeRenesas Electronics Corporation
InventorsMakoto Yabuuchi, Shinji Tanaka
Life of this patent
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Abstract
An object of the present invention is to provide a highly-reliable content addressable memory. Provided is a content addressable memory including: a plurality of CAM cells; a word line joined to the CAM cells; a plurality of bit lines joined to the CAM cells; a plurality of search lines joined to the CAM cells; a match line joined to the CAM cells; a match amplifier joined to the match line; and a selection circuit that can select the output of the match amplifier in accordance with the value of the word line.
Claims12
A content addressable memory comprising:
- a plurality of ternary content addressable memory (TCAM) cells;
- a first word line and a second word line coupled to the TCAM cells;
- a plurality of bit lines coupled to the TCAM cells;
- a plurality of search lines coupled to the TCAM cells;
- a match line coupled to the TCAM cells;
- a match amplifier coupled to the match line;
- and
- a selection circuit that selects an output of the match amplifier in accordance with a value of the first word line or the second word line.
A content addressable memory comprising:
- a plurality of ternary content addressable memory (TCAM) cells;
- a first word line and a second word line coupled to the TCAM cells;
- a plurality of bit lines coupled to the TCAM cells;
- a plurality of search lines coupled to the TCAM cells;
- a match line coupled to the TCAM cells;
- a match amplifier coupled to the match line;
- and
- a scan input circuit that supplies test search data to the search lines.
A content addressable memory comprising:
- a plurality of ternary content addressable memory (TCAM) cells;
- a plurality of word lines including a first word line and a second word line coupled to the TCAM cells;
- a plurality of bit lines coupled to the TCAM cells;
- a plurality of search lines coupled to the TCAM cells;
- a plurality of match lines coupled to the TCAM cells;
- and
- a match amplifying unit coupled to the match lines,
- wherein the match amplifying unit includes a plurality of latch circuits and a plurality of selection circuits,
- wherein each of the selection circuits includes a first input coupled to the corresponding match line and a second input coupled to the output of the corresponding latch circuit,
- wherein the latch circuits and the selection circuits configure a scan path between a scan input terminal and a scan output terminal, and
- wherein the selection circuit outputs the output of the corresponding latch circuit to a reading line in accordance with a selection level of the first word line or the second word line.
Dependencies are inferred from the claim text.