Device, system and method for providing on-chip test/debug functionality

A method at an integrated circuit (IC) chip, the method comprising:

• with a physical (PHY) layer of the IC chip, performing communications compatible with a universal serial bus standard that supports a data rate of 1.5 Megabits per second (Mbps) or more, wherein a link control layer of the IC chip is coupled between an interconnect and the PHY layer, the link control layer including a first link controller coupled to the interconnect via a host control interface, and further coupled to the interconnect via one of a device control interface and a debug controller coupled between the link control layer and the interconnect;
• configuring a test mode of the first link controller, including disabling one or more paths of communication between the link control layer and the PHY layer;
• receiving at the first link controller first signals sent, via the interconnect and the host control interface, from a test controller of the IC chip;
• and
• in response to the configuring and based on the receiving, emulating a communication received from a resource other than the test controller, including generating, by the first link controller, second signals based on the first signals and providing the second signals to the one of the device control interface and the debug controller.

A system comprising:

• an integrated circuit (IC) chip including:
• a physical (PHY) layer to perform communications compatible with a universal serial bus standard that supports a data rate of 1.5 Megabits per second (Mbps) or more;
• an interconnect;
• a link control layer coupled between the interconnect and the PHY layer, the link control layer including a first link controller coupled to the interconnect via a host control interface, and further coupled to the interconnect via one of a device control interface and a debug controller;
• and
• a test controller to configure a test mode of the first link controller and to send first signals to the first link controller via the interconnect and the host control interface, wherein based on the test mode, the first link controller to:
• disable one or more paths of communication between the link control layer and the PHY layer;
• and
• emulate a communication received from a resource other than the test controller, wherein the first link controller is configured to provide second signals, based on the first signals, to one of a device control interface and a debug controller coupled between the link control layer and the interconnect;
• and
• a display device coupled to the IC chip, the display device to display an image based on signals exchanged with the IC chip.