High speed chip substrate test fixture
AssigneeInternational Business Machines Corporation
InventorsLloyd A. Walls, Nam H. Pham, Jason R. Eagle, Nathan L. Dunfee, Pavel Roy Paladhi
Life of this patent
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Abstract
An apparatus, multi-layer semiconductor substrate and system for testing a high-speed signal through a printed circuit board is provided. Embodiment of the present invention provides an apparatus comprises a multi-layer substrate, one or more transmission lines disposed within the multi-layer substrate, one or more connectors attached to the multi-layer substrate for connecting one or more test cards, a lid, comprising one or more cutouts for the one or more connectors, a clamp for compressing the multi-layer substrate against the lid, and one or more high-speed connectors attached to the one or more test cards, respectively.
Claims20
An apparatus for testing a high-speed signal through a printed circuit board, the apparatus comprising:
- a multi-layer substrate, wherein the multilayer substrate comprises, a plurality of high-speed signal traces providing connections to an outer surface of an upper construct layer and an outer surface of a lower construct layer and passing through one or more intermediate construct layers;
- one or more transmission lines disposed within the multi-layer substrate;
- one or more connectors attached to the multi-layer substrate for connecting one or more test cards;
- a lid, comprising one or more cutouts for the one or more connectors, and the lid consisting of a fastened lid and a bonded lid held together, wherein the fastened lid comprises of an upper construct with of a C4 (controlled collapse chip connection) shape metallic pillar support located in the middle of the upper construct and the bonded lid comprising a lower construct with a four-sided polygon cut-out;
- a clamp for compressing the multi-layer substrate against a pressure place and lid;
- and
- one or more high-speed connectors attached to the one or more test cards, respectively.
A multi-layer semiconductor substrate for high speed circuit testing, the multi-layer semiconductor substrate comprising:
- an upper construct layer;
- a lower construct layer;
- one or more intermediate construct layers interposed between the upper construct layer and the lower construct layer;
- a plurality of high-speed signal traces providing connections to an outer surface of the upper construct layer and an outer surface of the lower construct layer and passing through the one or more intermediate construct layers;
- a lid, comprising one or more cutouts for one or more connectors, and the lid consisting of a fastened lid and a bonded lid held together, wherein the fastened lid comprises of an upper construct with of a C4 (controlled collapse chip connection) shape metallic pillar support located in the middle of the upper construct and the bonded lid comprising a lower construct with a four-sided polygon cut-out;
- one or more ground-return-vias or signal return vias connecting the upper construct layer and an adjacent intermediate construct layer;
- and
- one or more closed loop signal traces etched on the upper construct layer for minimizing electrical noise.
A system for testing a high speed signal through a printed circuit board, the system comprising:
- a multilayer substrate, wherein the multilayer substrate comprises, a plurality of high-speed signal traces providing connections to an outer surface of an upper construct layer and an outer surface of a lower construct layer and passing through one or more intermediate construct layers;
- a transmission line disposed within the multilayer substrate;
- one or more connectors attached to the multilayer substrate for connecting one or more test cards;
- a lid, comprising one or more cutouts for the one or more connectors and the lid consisting of a fastened lid and a bonded lid held together, wherein the fastened lid comprises of an upper construct with of a C4 (controlled collapse chip connection) shape metallic pillar support located in the middle of the upper construct and the bonded lid comprising a lower construct with a four-sided polygon cut-out;
- a clamp for compressing the multilayer substrate against the lid;
- one or more high-speed connectors attached to the one or more test cards, respectively;
- and
- a signal analyzer connected to the one or more high speed connectors.
Dependencies are inferred from the claim text.