Methods and apparatuses for signal translation in a buffered memory
AssigneeMicron Technology, Inc.
InventorsTimothy M. Hollis, Dean Gans, Randon Richards, Bruce W. Schober
Life of this patent
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Abstract
According to one embodiment, A data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.
Claims20
A apparatus comprising:
- a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol;
- a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, the second input/output circuit further comprises a multilevel decoder circuit configured to decode the second signal to provide a plurality of parallel data bits;
- and
- a deserializer circuit configured to convert the plurality of parallel data bits to a plurality of serial data bits, wherein the deserializer circuit comprises:
- a first passgate configured to provide a first serial data bit of the plurality of serial data bits at a first time, and
- a second passgate configured to provide a second serial data bit of the plurality of serial data bits at a second time.
An apparatus comprising:
- a first data bus configured to provide a binary signal;
- and
- a data buffer coupled to the first data bus, the data buffer configured to receive the binary signal and to convert the binary signal to a multilevel signal, wherein the data buffer comprises a conversion circuit configured to convert binary signals to multilevel signals and to convert multilevel signals to binary signals, wherein the conversion circuit comprises:
- a deserialization circuit comprising a first latch configured to latch a first serial data bit received on the first data bus at a first time and a second latch configured to latch a second serial data bit received on the first data bus at a second time, and
- a parallel data synchronization circuit configured to synchronize the first serial data bit and the second data bit to generate first and second parallel data bits, wherein a multilevel transmitter circuit is configured to provide a multilevel signal based on the first and second parallel data bits.
A method comprising:
- receiving, at a data buffer, a binary data signal comprising a plurality of serial data bits;
- converting, by the data buffer, the plurality of serial data bits to a plurality of parallel data bits;
- latching, via a first latch, a first serial data bit of the plurality of serial data bits at a first time;
- latching, via a second latch, a second serial data bit of the plurality of serial data bits at a second time;
- and
- synchronizing the first serial data bit and the second data bit to generate first and second parallel data bits of the plurality of data bits, wherein a multilevel transmitter circuit is configured to provide a multilevel signal based on the first and second parallel data bits.
Dependencies are inferred from the claim text.