Nonvolatile semiconductor storage device with cell transistors
AssigneeRohm Co., Ltd.
InventorsKazuhisa Ukai, Koji Nigoriike
Life of this patent
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Abstract
A nonvolatile semiconductor storage device includes a plurality of cell transistor pairs including a pair of cell transistors sharing a first node connected to a bit line or a source line, and a dummy gate line laid in parallel with gate lines of the cell transistors, the dummy gate line applying an off voltage to a dummy transistor between the cell transistor pairs. The gate lines and the dummy gate line may be laid at equal intervals. A plurality of impurity diffusion layers corresponding to the first node and second nodes of the cell transistors may be formed at equal intervals in a continuous active region.
Claims17
A nonvolatile semiconductor storage device comprising:
- a first pair of cell transistors sharing a first node connected to one of a bit line and a source line, wherein the first pair of cell transistors forms a first pair of mask read only memory cells;
- a second pair of cell transistors sharing a second node connected to the one of the bit line and the source line, wherein the second pair of cell transistors forms a second pair of mask read only memory cells;
- transistor gate lines connected to the first pair of cell transistors and the second pair of cell transistors, respectively;
- a dummy transistor arranged between the first pair of cell transistors and the second pair of cell transistors;
- and
- a dummy gate line laid in parallel with the transistor gate lines, wherein
- the dummy gate line is connected to the dummy transistor, and
- the dummy gate line applies an off voltage to the dummy transistor.
A nonvolatile semiconductor storage device comprising:
- a first pair of cell transistors;
- first transistor gate lines connected to the first pair of cell transistors, respectively;
- a dummy transistor next to the first pair of cell transistors;
- and
- a dummy gate line laid in parallel with the first transistor gate lines, wherein
- the dummy gate line is connected to the dummy transistor,
- the dummy gate line applies an off voltage to the dummy transistor, and
- an interval between the first transistor gate lines is equal to an interval between the dummy gate line and one of the first transistor gate lines neighboring the dummy gate line.
A nonvolatile semiconductor storage device comprising:
- a first cell transistor;
- a second cell transistor;
- transistor gate lines connected to the first cell transistor and the second cell transistor, respectively;
- a dummy transistor arranged between the first cell transistor and the second cell transistor;
- and
- a dummy gate line laid in parallel with the transistor gate lines, wherein
- the dummy gate line applies an off voltage to the dummy transistor,
- the first cell transistor includes an impurity diffusion layer,
- the dummy transistor includes an impurity diffusion layer continuously formed with the impurity diffusion layer of the first cell transistor, and
- the second cell transistor includes an impurity diffusion layer, and
- the dummy transistor further includes an impurity diffusion layer continuously formed with the impurity diffusion layer of the second cell transistor.
Dependencies are inferred from the claim text.