Multi-threshold voltage gate-all-around field-effect transistor devices with common gates

A method for fabricating a semiconductor device, comprising:

• forming a first nanosheet stack structure of a first nanosheet field-effect transistor device on a semiconductor substrate, wherein the first nanosheet stack structure comprises a first stack of alternating semiconductor layers which comprises a plurality of first sacrificial nanosheet layers, and plurality of first active nanosheet channel layers, wherein each first active nanosheet channel layer is disposed between first sacrificial nanosheet layers in the first nanosheet stack structure, and wherein each first sacrificial nanosheet layer has a first thickness which defines a first channel spacing between the first active nanosheet channel layers of the first nanosheet stack structure;
• forming a second nanosheet stack structure of a second nanosheet field-effect transistor device on the semiconductor substrate, wherein the second nanosheet stack structure comprises a second stack of alternating semiconductor layers which comprises a plurality of second sacrificial nanosheet layers, and a plurality of second active nanosheet channel layers, wherein each second active nanosheet channel layer is disposed between second sacrificial nanosheet layers in the second nanosheet stack structure, and wherein each second sacrificial nanosheet layer has a second thickness which defines a second channel spacing between the second active nanosheet channel layers of the second nanosheet stack structure, wherein the second channel spacing is greater than the first channel spacing;
• forming first and second dummy gates over the first and second nanosheet stack structures, respectively, to define respective first and second gate regions;
• removing the first and second dummy gates to open the first and second gate regions and expose portions of the first and second nanosheet stack structures within the first and second gate regions;
• removing the first and second sacrificial nanosheet layers exposed in the first and second gate regions to release the first and second active nanosheet channel layers of the first and second nanosheet stack structures and form spaces between the first active nanosheet channel layers with the first channel spacing and form spaces between the second active nanosheet channel layers with the second channel spacing;
• and
• concurrently forming a first high-k dielectric/metal gate structure and a second high-k dielectric/metal gate structure within the first gate region and the second gate region, respectively;
• wherein the first nanosheet field-effect transistor device has a first threshold voltage as a result of the first high-k dielectric/metal gate structure formed around the first active channel layers that are separated by the first channel spacing;
• and
• wherein the second nanosheet field-effect transistor device has a second threshold voltage, which is different from the first threshold voltage, as a result of the second high-k dielectric/metal gate structure formed around the second active channel layers that are separated by the second channel spacing.

A semiconductor integrated circuit device, comprising:

• a first field-effect transistor device disposed on a semiconductor substrate, wherein the first field-effect transistor device comprises (i) a plurality of first active channel layers that are separated by a first channel spacing and (ii) a first gate sidewall spacer which defines a first gate region of the first field-effect transistor device;
• a second field-effect transistor device disposed on the semiconductor substrate, wherein the second field-effect transistor device comprises (i) a plurality of second active channel layers that are separated by a second channel spacing, wherein the second channel spacing is greater than the first channel spacing, and (ii) a second gate sidewall spacer which defines a second gate region of the second field-effect transistor device;
• and
• common first and second high-k dielectric/metal gate structures disposed within the first and second gate regions, respectively, of the first and second field-effect transistor devices;
• wherein the first field-effect transistor device has a first threshold voltage as a result of the first high-k dielectric/metal gate structure formed around the first active channel layers that are separated by the first channel spacing;
• and
• wherein the second field-effect transistor device has a second threshold voltage, which is different from the first threshold voltage, as a result of the second high-k dielectric/metal gate structure formed around the second active channel layers that are separated by the second channel spacing.