# US 10,699,948 B2 · Plated metallization structures

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- Number: US 10,699,948 B2
- Document ID: US10699948B2
- Status: Granted
- Kind: B2
- Application number: 15/810,836
- Filed: 2017-11-13
- Published: 2019-05-16
- Granted: 2020-06-30
- Earliest claimed: 2017-11-13
- Assignees: Analog Devices Global Unlimited Company
- Applicants: Analog Devices Global Unlimited Company
- Inventors: Jan Kubik; Bernard P. Stenson; Michael Noel Morrissey
- Web page: https://patentgrep.com/patent/US10699948B2

## CPC

- H10W 20/063: {by forming conductive members before forming protective insulating material}
- C23C 18/1605: {by masking}
- C23C 18/1651: {Two or more layers only obtained by electroless plating}
- C25D 5/022: {using masking means}
- C25D 5/10: Electroplating with more than one layer of the same or of different metals (for bearings C25D7/10)
- C25D 7/123: {Semiconductors first coated with a seed layer or a conductive layer}
- H05K 3/184: {using masks}
- H05K 3/244: {Finish plating of conductors, especially of copper conductors, e.g. for pads or lands (selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3465)}
- H05K 3/422: {characterised by electroless plating method; pretreatment therefor}
- H10D 1/20: Inductors
- H10P 14/47: Electrolytic deposition, i.e. electroplating; Electroless plating
- H10P 76/403: {for lift-off processes}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/039: {also covering sidewalls of the conductive structures}
- H10W 20/043: {for electroplating}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H05K 1/0265: {characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections}
- H05K 3/188: {by direct electroplating}
- H05K 3/424: {by direct electroplating}
- H05K 2201/0367: Metallic bump or raised conductor not used as solder bump
- H05K 2201/0391: Using different types of conductors
- H05K 2201/09563: Metal filled via
- H05K 2201/096: Vertically aligned vias, holes or stacked vias
- H05K 2201/09845: Stepped hole, via, edge, bump or conductor
- H05K 2203/0716: Metallic plating catalysts, e.g. for direct electroplating of through holes; Sensitising or activating metallic plating catalysts
- H05K 2203/1407: Applying catalyst before applying plating resist
- H05K 2203/1423: Applying catalyst before etching, e.g. plating catalyst in holes before etching circuit
- H05K 2203/1476: Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- C25D: PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

## Claims

### Claim 1

An integrated circuit device, comprising:
a substrate;
one or both of a first conductive barrier layer and a seed layer formed on a major surface of the substrate; and
a metallization structure comprising a first metal feature having top and side surfaces above the one or both of the first conductive barrier layer and the seed layer that are encapsulated by a second metal, wherein each of the first metal feature and the second metal is formed over the one or both of the first conductive barrier layer and the seed layer that are patterned to be laterally coextensive with the metallization structure, wherein the second metal has a conformal thickness profile characteristic of a plated layer across the top surface of the first metal feature, wherein a ratio of a thickness of the first metal feature to a thickness of the second metal is between about 0.5 and 1.5, and wherein the metallization structure forms a line elongated in a direction substantially parallel to the major surface of the substrate and has a thickness exceeding about 10 microns.

### Claim 2 (depends on 1)

The integrated circuit device of claim 1, wherein the metallization structure has a width which remains constant or decreases from a base portion towards an upper surface.

### Claim 3 (depends on 2)

The integrated circuit device of claim 2, wherein the second metal encapsulates the first metal feature and laterally extends outside of the first metal feature such that the metallization structure comprises a raised portion formed by the second metal encapsulating the first metal feature and further comprises a portion electroplated directly on the conductive barrier layer or the seed layer.

### Claim 4 (depends on 3)

The integrated circuit device of claim 3, further comprising a conductive via electrically contacting the raised portion through one of more dielectric layers formed over the metallization structure.

### Claim 5 (depends on 3)

The integrated circuit device of claim 3, wherein the first metal feature and the second metal are formed of different metals.

### Claim 6 (depends on 5)

The integrated circuit device of claim 5, wherein a second conductive barrier layer interposed between the first metal feature and the second metal encapsulates the first metal feature, wherein the second conductive barrier layer serves as a diffusion barrier for suppressing diffusion of atoms of the first metal feature.

### Claim 7 (depends on 6)

The integrated circuit device of claim 6, wherein the first metal feature comprises copper.

### Claim 8 (depends on 7)

The integrated circuit device of claim 7, wherein a third conductive barrier layer is interposed between the first metal feature and the substrate.

### Claim 9 (depends on 5)

The integrated circuit device of claim 5, further comprising a third conductive barrier layer interposed between the first conductive barrier layer and the first metal feature.

### Claim 10 (depends on 5)

The integrated circuit device of claim 5, wherein the metallization structure further comprises a third metal encapsulating the second metal and contacting the first conductive barrier layer or the seed layer.

### Claim 11 (depends on 1)

The integrated circuit device of claim 1, wherein the second metal encapsulates the first metal feature to form the metallization structure wider and thicker than the first metal feature.

### Claim 12 (depends on 11)

The integrated circuit device of claim 11, wherein the second metal has thicknesses over a top surface and side surfaces of the first metal feature that are about the same.

### Claim 13 (depends on 1)

The integrated circuit device of claim 1, wherein the metallization structure is formed at a single metallization level.

### Claim 14 (depends on 1)

The integrated circuit device of claim 1, wherein the first metal feature has a width which remains substantially constant or decreases from a base portion towards an upper surface.

### Claim 15 (depends on 1)

The integrated circuit device of claim 1, wherein the first metal feature has a width at an upper portion that is wider than a width at a base portion.

### Claim 16 (depends on 1)

The integrated circuit device of claim 1, wherein the first metal feature and the second metal comprise the same metal.

### Claim 17 (depends on 1)

The integrated circuit device of claim 1, wherein each of the first metal feature and the second metal contacts the same one of the first conductive barrier layer or the seed layer.

### Claim 18 (depends on 1)

The integrated circuit device of claim 1, wherein the first metal feature comprises gold or copper.

### Claim 19 (depends on 18)

The integrated circuit device of claim 18, wherein the second metal comprises a different one of gold or copper.