Virtualization of a reconfigurable data processor

A reconfigurable data processor, comprising:

• an array of configurable units including a plurality of tiles of configurable units on one die or a multichip module;
• a bus system connected to the array of configurable units, comprising boundary switches on tile boundaries between the tiles including circuits to configurable partition the bus system on the tile boundaries, and block communications via the bus system between configurable units within a particular tile and configurable units outside the particular tile;
• and
• a plurality of memory access controllers connected to the bus system, memory access controllers in the plurality of memory access controllers being configurable to confine access to memory outside the array of configurable units originating from within corresponding tiles to memory space allocated to the corresponding tile in the memory outside the array of configurable units, and wherein at least one memory access controller in the plurality of memory access controllers is operatively coupled to each tile in the plurality of tiles.

A method for configuring a reconfigurable data processor, comprising an array of configurable units and a bus system connected to the array of configurable units on one die or multichip module;

• comprising
• partitioning the array of configurable units on the die or multichip module into a plurality of sets of configurable units, by blocking communications via the bus system between configurable units within a particular set and configurable units outside the particular set;
• and
• confining access to memory outside the array of configurable units originating from within the particular set to memory space allocated to the particular set in the memory outside the array of configurable units.