Impedance adjusting circuit and integrated circuit including the same

An integrated circuit, comprising:

• a first node coupled to a resistor;
• a first impedance unit having an impedance value determined based on a first impedance code and coupled between a first voltage terminal and a second node;
• a first switching unit suitable for electrically connecting the first node and the second node to each other in response to a clock;
• a first average voltage unit suitable for generating an average voltage of the first node;
• a first comparison unit suitable for comparing the average voltage of the first node with a first reference voltage to produce a comparison result of the first comparison unit;
• a first code generation unit suitable for generating the first impedance code in response to the comparison result of the first comparison unit;
• a second impedance unit having an impedance value determined based on a second impedance code and coupled between a second voltage terminal and a third node;
• a second switching unit suitable for electrically connecting the first node and the third node to each other in response to the clock;
• a second comparison unit suitable for comparing the average voltage of the first node with a second reference voltage to produce a comparison result of the second comparison unit;
• a second code generation unit suitable for generating the second impedance code in response to the comparison result of the second comparison unit;
• a first output driver circuit having a driving force controlled based on the first impedance code and the second impedance code to output first output data to a fourth node;
• a second output driver circuit having a driving force controlled based on the first impedance code and the second impedance code to output second output data to a fifth node;
• a third switching unit suitable for electrically connecting the fourth node and an output node to each other in response to the clock;
• and
• a fourth switching unit suitable for electrically connecting the fifth node and the output node to each other in response to an inverted clock.

An integrated circuit, comprising:

• a first node coupled to a resistor;
• a first impedance unit having an impedance value determined based on a first impedance code and coupled between a first voltage terminal and a second node;
• a first switching unit suitable for electrically connecting the first node and the second node to each other in response to a clock;
• a first average voltage unit suitable for generating an average voltage of the first node;
• a first comparison unit suitable for comparing the average voltage of the first node with a first reference voltage to produce a comparison result of the first comparison unit;
• a first code generation unit suitable for generating the first impedance code in response to the comparison result of the first comparison unit;
• a second impedance unit having an impedance value determined based on the first impedance code and coupled between the first voltage terminal and a third node;
• a third impedance unit having an impedance value determined based on a second impedance code and coupled between a second voltage terminal and a fourth node;
• a second switching unit suitable for electrically connecting a fifth node and the third node to each other in response to the clock;
• a third switching unit suitable for electrically connecting the fifth node and the fourth node to each other in response to the clock;
• a second average voltage unit suitable for generating an average voltage of the fifth node;
• a second comparison unit suitable for comparing the average voltage of the fifth node with a second reference voltage to produce a comparison result of the second comparison unit;
• a second code generation unit suitable for generating the second impedance code in response to the comparison result of the second comparison unit;
• a first output driver circuit having a driving force controlled based on the first impedance code and the second impedance code to output first output data to the fourth node;
• a second output driver circuit having a driving force controlled based on the first impedance code and the second impedance code to output second output data to the fifth node;
• a fourth switching unit suitable for electrically connecting the fourth node and an output node to each other in response to the clock;
• and
• a fifth switching unit suitable for electrically connecting the fifth node and the output node to each other in response to an inverted dock.