3D static RAM core cell having vertically stacked structure, and static RAM core cell assembly comprising same

A method of manufacturing a 3D static RAM core cell having a vertically stacked structure containing thin-film transistors, consisting essentially of:

• (a) forming a first transistor layer including two of the thin-film transistors;
• (b) after forming the first transistor layer, forming a second transistor layer including two of the thin-film transistors on the first transistor layer;
• and
• (c) after forming the second transistor layer, forming a third transistor layer including two of the thin-film transistors on the second transistor layer,
• wherein the step (a) consists of:
• (a-1) forming a first source electrode and a first drain electrode on a substrate through printing;
• (a-2) forming a first electrode channel film comprising a first organic semiconductor between the first source electrode and the first drain electrode through printing;
• (a-3) forming a first insulating film on the first electrode channel film through deposition;
• and
• (a-4) forming a first gate electrode on the first insulating film through printing,
• wherein the first electrode channel film, the first insulating film, and the first gate electrode are sequentially disposed upwards,
• the step (b) consists of:
• (b-1) forming a second source electrode and a second drain electrode on the first transistor layer through printing;
• (b-2) forming a second electrode channel film comprising a second organic semiconductor between the second source electrode and the second drain electrode through printing;
• (b-3) forming a second insulating film on the second electrode channel film through deposition;
• and
• (b-4) forming a second gate electrode on the second insulating film through printing,
• wherein, the second electrode channel film, the second insulating film, and the second gate electrode are sequentially disposed upwards,
• the step (c) consists of:
• (c-1) forming a third insulating film on the second gate electrode through deposition;
• (c-2) forming a third source electrode and a third drain electrode on the third insulating film through printing;
• and
• (c-3) forming a third electrode channel film comprising a third organic semiconductor between the third source electrode and the third drain electrode through printing,
• wherein, the third electrode channel film and the third insulating film are sequentially disposed downwards, and
• at least one electrode of the first transistor layer and at least one electrode of the second transistor layer being electrically connected to each other, and at least one electrode of the second transistor layer and at least one electrode of the third transistor layer being electrically connected to each other.