Methods and apparatus for an amplifier integrated circuit
AssigneeSemiconductor Components Industries, LLC
InventorTsutomu Murata
Life of this patent
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Abstract
Various embodiments of the present technology may provide methods and apparatus for an amplifier integrated circuit. The amplifier integrated circuit may provide a low gain bandwidth product to amplify at a higher speed and a high gain bandwidth product to amplify at a lower speed. The amplifier integrated circuit may achieve the low and high gain bandwidth product by generating a first current and a second current through a plurality of sets of series-connected transistors and operating a plurality of switches.
Claims19
An amplifier integrated circuit (IC), comprising:
- a first set of series-connected transistors connected to:
- a first node having a supply voltage potential;
- a second node having a first bias potential;
- a third node having a second bias potential;
- and
- a fourth node having a third bias potential;
- wherein the first, second, and third bias potentials have values that are different from each other;
- a second set of series-connected transistors connected:
- in parallel with the first set of transistors;
- and
- to the first node;
- a third set of series-connected transistors connected to the first node;
- a fourth set of series-connected transistors connected:
- in parallel with the third set of transistors;
- and
- to the first node;
- a first switching circuit connecting the first set of transistors to the second set of transistors;
- and
- a second switching circuit connecting the third set of transistors to the fourth set of transistors.
A method for providing an amplifier integrated circuit with variable gain bandwidth product, comprising:
- generating a first output with the amplifier integrated circuit according to a first gain bandwidth product, comprising:
- generating a first current through a first set of series-connected transistors and a fourth set of series-connected transistors, comprising:
- applying a plurality of bias potentials to the first and fourth sets of series-connected transistors, wherein bias potentials have different values from each other;
- and
- applying a supply voltage potential to the first and fourth sets of series-connected transistors;
- and
- generating a second output with the amplifier integrated circuit according to a second gain bandwidth product, comprising:
- generating the first current through the first set of series-connected transistors by applying the plurality of bias potentials and the supply voltage potential to the first set of series-connected transistors;
- and
- generating a second current through a second set of series-connected transistors and a third set of series-connected transistors, comprising:
- applying the supply voltage potential to the second and third sets of series-connected transistors;
- connecting the first set of transistors to the second set of transistors;
- and
- connecting the third set of transistors to the fourth set of transistors.
A system, comprising:
- a sensor configured to generate sensor data;
- an amplifier integrated circuit (IC) comprising:
- a main input terminal configured to receive the sensor data;
- and
- a main output terminal;
- wherein the amplifier IC is configured to:
- generate a first output signal according to a first gain bandwidth product;
- and
- generate a second output signal according to a second gain bandwidth product and in sequence with the first output signal while the amplifier IC is ON, wherein the second gain bandwidth is less than the first gain bandwidth product;
- and
- a switched capacitor circuit connected to the main output terminal and configured to charge according to the first and second output signals.
Dependencies are inferred from the claim text.