Method and apparatus for forming contacts on an integrated circuit die using a catalytic adhesive

A process for forming an integrated circuit device, the process operative on an integrated circuit chip having electrically conductive lands on a first surface, the first surface coated with a catalytic adhesive thereby forming a second surface above the first surface, said second surface having a reduced density of catalytic particles in a region extending from said second surface to an exclusion depth below said second surface compared to other regions of the catalytic adhesive, the process comprising:

• applying a catalytic adhesive to an integrated circuit chip;
• curing the catalytic adhesive;
• forming apertures into the catalytic adhesive in locations corresponding to integrated circuit lands, said apertures thereby exposing said catalytic particles of said catalytic adhesive and said integrated circuit lands;
• forming channels in the catalytic laminate to a depth below the exclusion depth and leading to said apertures and also to optional connection regions on said second surface;
• performing an electroless plating operation until said channels and apertures are in electrical contact with said integrated circuit lands and said optional connection regions.

A process for forming an integrated circuit package, the process operative on an integrated circuit with conductive lands, the process comprising:

• applying a catalytic adhesive to a surface of the integrated circuit, said catalytic adhesive having catalytic particles below an exclusion depth;
• forming apertures in said catalytic adhesive adjacent to said conductive lands;
• forming device leads in the catalytic adhesive;
• forming channels having a depth greater than the exclusion depth in the adhesive which interconnect at least one said integrated circuit land to at least one device terminal;
• electroless plating said integrated circuit package, thereby connecting said device terminals and said at least one integrated circuit conductive land.