Method and device for testing a chain of flip-flops
AssigneeSTMicroelectronics (Crolles 2) SAS
InventorsSylvain Clerc, Gilles Gasiot
Life of this patent
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Abstract
A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.
Claims18
An electronic device for testing a chain of flip-flops, the electronic device comprising:
- a processing circuit having an input and an output;
- a generating circuit configured to generate a reference signal from a cyclic test pattern and provide the reference signal to a first flip-flop of the chain of flip-flops and to the input of the processing circuit;
- and
- wherein the processing circuit is configured to receive a flip-flop output from a last flip-flop of the chain of flip-flops, to compare the flip-flop output to the reference signal, and to generate an output signal at its output indicating whether at least one flip-flop of the chain of flip-flops is defective.
An electronic device for testing a chain of flip-flops, the electronic device comprising:
- a generation circuit comprising:
- a plurality of reference generation circuits, each configured to generate a different intermediate reference signal from a cyclic test pattern;
- wherein the plurality of reference generation circuits are replicas of one another;
- and
- a majority vote circuit receiving the different intermediate reference signals from each of the plurality of reference generation circuits, the majority vote circuit configured to generate a reference signal as matching a majority of the different intermediate reference signals;
- wherein the chain of flip-flops receives the reference signal from the majority vote circuit and produces a flip-flop output as the reference signal propagates through the chain of flip-flops;
- and
- a processing circuit comprising:
- a plurality of intermediate processing circuits, each configured to receive the flip-flop output from a last flip-flop of the chain of flip-flops, to compare the flip-flop output to the reference signal, and to generate a different intermediate output signal at an output indicating whether at least one flip-flop of the chain of flip-flops is defective;
- wherein the plurality of intermediate processing circuits are replicas of one another;
- a majority vote circuit receiving the different intermediate output signals from each of the plurality of intermediate processing circuits, the majority vote circuit configured to generate an output signal as matching a majority of the different intermediate output signals;
- and
- wherein the output signal indicates whether at least one flip-flop of the chain of flip-flops is defective.
Dependencies are inferred from the claim text.