Watchdog for monitoring a processor

A method for monitoring a processor by a watchdog comprising a clock generator, a result memory having n result memory cells, wherein n is a positive integral number larger than 1, a first stimulating portion of the watchdog (QSTM) for transmission of messages from the watchdog to the processor, a first evaluation portion of the watchdog (AVAL) for evaluation of answers of the processor which are transmitted by the processor to the watchdog in response to the messages from the watchdog, and comprising a second evaluation portion of the watchdog (VAL) for evaluation of buffered information items (Inf1 to Infn) of the result memory, wherein, in the method

• n information items (Inf1 to Infn) are buffered into the n result memory cells of the result memory, wherein the n buffered information items (Inf1 to Infn) are continuously numbered from 1 to n, wherein each of the n buffered information items (Inf1 to Infn) is assigned to a respective result memory position of n result memory positions which are continuously numbered from 1 to n, and wherein each of the n buffered information items (Inf1 to Infn) comprises at least one first information portion,
• the watchdog is operative to transmit messages to the processor that can pertain to the processor itself and to further system components,
• the processor is operative to transmit answers to the watchdog depending on the messages,
• the first evaluation portion of the watchdog is operative to assess each of the answers of the processor as “correct” or “not correct”,
• wherein a respective answer is “correct”
• if a content of the respective answer coincides with at least one possible expected content, and
• if the answer is received by the watchdog within a predetermined reception time period, and
• wherein the respective answer is “not correct”
• if the content of the respective answer does not coincide with at least one possible expected content, or
• if the respective answer is not received by the watchdog within the predetermined reception time period, and
• in the result memory, after an end of the predetermined reception time period or after a respective end of each predetermined reception time period or after an end of a plurality of predetermined reception time periods,
• a buffered information item (e.g. Infj) at a j-th result memory position in a corresponding result memory cell of the result memory is deleted from the result memory, wherein 1≤j≤n,
• the remaining [n−1] buffered information items (Infk), wherein 1≤j≤n and k≠j, are shifted from the respective k-th result memory position (pk, with 1≤j≤m and k≠j) to another result memory position (pk′, with k′≠k and 1≤k′≤n), and
• at least as a new first portion of the j′-th buffered information item (e.g. Infj′) at a result memory position into which none of the remaining [n−1] buffered information items (Inf1 to Infn) has been shifted, there is used, in correspondence to a value for “correct” or for “not correct”, at least a result of the evaluation of the respective answer or the respective answers of the processor received before the end of the reception time period or periods,
• wherein the second evaluation portion of the watchdog (VAL), if buffered information items of the n buffered information items (Inf1 to Infn) in the result memory cells of the result memory comprise an identifiable predetermined pattern, generates at least one control signal adapted to change a state of the processor, or generates a signal from which the control signal is derived.

A method for monitoring a processor by a watchdog comprising a clock generator, a result memory having n result memory cells, wherein n is a positive integral number larger than 1, a first stimulating portion of the watchdog (QSTM) for transmission of messages from the watchdog to the processor, a first evaluation portion of the watchdog (AVAL) for evaluation of answers of the processor which are transmitted by the processor to the watchdog in response to the messages from the watchdog, and comprising a second evaluation portion of the watchdog (VAL) for evaluation of buffered information items (Inf1 to Infn) of the result memory, comprising:

• presetting, by the clock generator, a predetermined reception time period for an answer (ANS) of the processor to the watchdog;
• transmitting, from the watchdog to the processor, one or a plurality of messages (MSG) with respective contents which can pertain to the processor and/or to further system components,
• responding to the message in form of the answer to the watchdog, performed by the processor depending on at least a content of one of the messages,
• evaluating the answer of the processor to the watchdog as “correct” or “not correct”, performed by the watchdog, for generating an evaluation result,
• wherein the answer is “correct”
• if a content of the answer coincides with at least one possible expected content, and
• if the answer is received by the watchdog within the predetermined reception time period (b), and
• wherein an answer is “not correct”
• if the content of the answer does not coincide with at least one possible expected content, or
• if the answer is not received by the watchdog within the predetermined reception time period,
• changing a content of a result memory with n buffered information items (Inf1 to Infn), wherein each of the n buffered information items (Inf1 to Infn) comprises at least one respective first information portion and is assigned to a respective result memory position, wherein n is an integer larger than 1, wherein the changing is performed
• temporally after reception of the respective answer by the watchdog or
• temporally after an end of the predetermined reception time period
• by
• deletion of at least one buffered information item (Infk) of the n information items (Inf1 to Infn), and
• changing at least one logical result memory position of the at least one buffered information item (Infj) of the n buffered information items (Inf1 to Infn) in a result memory and
• use of a result of the evaluation of the at least one received answer as a new first information portion of a new buffered information item (Infj) in the result memory,
• evaluation of the buffered information items (Inf1 to Infn) of the result memory (ES) by the second evaluation portion of the watchdog (VAL) by generating an evaluation result depending on identifiable predetermined patterns from the buffered information items (Inf1 to Infn) of the n buffered information items (Inf1 to Infn), and
• upon identification of a predetermined pattern, generation of at least one control signal adapted to change a state of the processor, or generation of a signal from which the control signal is derived.