Programmable multiply-add array hardware
AssigneeAlibaba Group Holding Limited
InventorsLiang Han, Xiaowei Jiang
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Abstract
An integrated circuit including a data architecture including N adders and N multipliers configured to receive operands. The data architecture receives instructions for selecting a data flow between the N multipliers and the N adders of the data architecture. The selected data flow includes the options: (1) a first data flow using the N multipliers and the N adders to provide a multiply-accumulate mode and (2) a second data flow to provide a multiply-reduce mode.
Claims14
A method for specifying functionalities to be performed on a data architecture including N adders and N multipliers configured to receive operands, the method comprising:
- receiving instructions for the data architecture to operate in one of a multiply-reduce mode or a multiply-accumulate mode, wherein the N multipliers and at least some of the N adders of the data architecture are used both in the multiply-reduce mode and the multiply-accumulate mode;
- and
- selecting, based on the instructions, a data flow between the N multipliers and the at least some of the N adders of the data architecture,
- wherein the N multipliers includes a first multiplier of which output data is provided to a first adder among the at least some of the N adders in the multiply-reduce mode and to a second adder among the at least some of the N adders in the multiply-accumulate mode.
An integrated circuit comprising:
- a data architecture including N adders and N multipliers configured to receive operands, wherein the data architecture receives instructions for selecting a data flow between the N multipliers and at least some of the N adders of the data architecture, the selected data flow including the options:
- a first data flow using the N multipliers and the N adders to provide a multiply-accumulate mode;
- and
- a second data flow to provide a multiply-reduce mode,
- wherein the N multipliers and the at least some of the N adders are used both in the first data flow and the second data flow, and
- wherein the N multipliers includes a first multiplier of which output data is provided to a first adder among the at least some of the N adders in the first data flow and to a second adder among the at least some of the N adders in the second data flow.
A non-transitory computer-readable storage medium that stores a set of instructions that is executable by at least one processor of a device to cause the device to perform a method for specifying functionalities to be performed on a data architecture including N adders and N multipliers configured to receive operands, the method comprising:
- receiving instructions for the data architecture to operate in one of a multiply-reduce mode or a multiply-accumulate mode, wherein the N multipliers and at least some of the N adders of the data architecture are used both in the multiply-reduce mode and the multiply-accumulate mode;
- and
- selecting, based on the instructions, a data flow between the N multipliers and the at least some of the N adders of the data architecture,
- wherein the N multipliers includes a first multiplier of which output data is provided to a first adder among the at least some of the N adders in the multiply-reduce mode and to a second adder among the at least some of the N adders in the multiply-accumulate mode.
Dependencies are inferred from the claim text.