Systems for mechanical logic based on additively manufacturable micro-mechanical logic gates

A mechanical logic OR gate system comprising:

• a first fixed structure;
• a second fixed structure spaced apart from the first fixed structure;
• a central body acting as an output element, which is positioned between the first and second fixed structures;
• a first input element supported by at least one first bi-stable flexure beam between a portion of the central body and the first fixed structure;
• a second input element supported by at least one second bi-stable flexure beam between the central body and the second fixed structure;
• at least one third bi-stable flexure beam connecting the first input element to the central body;
• at least one fourth bi-stable flexure beam connecting the second input element to the central body;
• and
• wherein an input applied to either one of the first or second input elements to cause movement from a logic 0 level position to a logic 1 level position of either one of the input elements, causes movement of the central body from a logic 0 level position to a logic 1 level position.

A mechanical logic NAND gate system comprising:

• a mechanical OR gate subsystem having first and second input elements and an output element;
• a mechanical NOT gate having first and second mechanical NOT gates, each of the first and second mechanical NOT gates including a plurality of bi-stable buckling structures supported from a plurality of stationary structures;
• the first mechanical NOT gate including an input element and an output element, the output element of the first mechanical NOTgate coupled to the first input element of the OR gate subsystem;
• the second mechanical NOT gate including an input element and an output element, the output element of the second mechanical NOT gate coupled to the second input element of the OR gate subsystem;
• and
• wherein a logic 1 level signal applied to one or the other of the input elements of the first or second mechanical NOT gates causes movement of the output element of the mechanical OR gate from a logic 0 level position to a logic 1 level position, and movement of both of the input elements of the first and second mechanical NOT gates to the logic 1 level position causes movement of the output element of the OR gate subsystem to the logic 0 level position.