Methods and circuits for generating parallel pseudorandom binary sequences

A circuit for generating M parallel pseudorandom binary sequences (PRBSs) each comprising a pseudorandom sequence of 2n−1 bits, M and n being integers, the circuit comprising:

• a pre-loading circuit configured for loading an initial M-bit word, the initial M-bit word comprising M sequential bits selected from a pre-determined PRBS-n sequence, wherein n>1 and M>n;
• a plurality of logic gates configured for generating a next M-bit word using at least n+1 of the M sequential bits of the initial M-bit word and then repeatedly generating the next M-bit word from a previous M-bit word using the at least n+1 of M sequential bits of the previous M-bit word, resulting in M parallel sequences of the PRBS-n sequence;
• and
• an output circuit configured for transmitting the generated next M-bit words on a M-bit wide parallel bus.

A method for designing a circuit for generating M parallel pseudorandom binary sequences (PRBSs) each comprising a pseudorandom sequence of 2n−1 bits, the method comprising:

• generating a tap table specifying, for each bit position of M bits of a next M-bit word, a plurality of taps to n sequential bits of a previous M-bit word to create M parallel sequences of a PRBS-n sequence, wherein n>1 and M>n;
• identifying a plurality of bit positions each having more than two taps to the n sequential bits of the previous M-bit word;
• for each bit position having more than two taps, searching, using at least one processor, for equivalent tap substitutions using at least one more bit from the previous M-bit word in addition to the n sequential bits;
• and
• specifying a plurality of logic gates for the circuit using the tap table and at least one equivalent tap substitution found while searching for equivalent tap substitutions.