US 10,673,440 B1Granted

Unified programmable computational memory and configuration network

AssigneeXilinx, Inc.

InventorRafael C. Camarota

Life of this patent

Estimating the term…

Loading patent…

Abstract

Examples generally relate a programmable device having a unified programmable computational memory (PCM) and configuration network. In an example, a programmable device includes a die that includes a PCM integrated circuit having a PCM tile. The PCM tile includes a configuration memory (CM) and combinational logic (CL). The CM is capable of storing configuration data received via a node in the PCM tile. The CL is configured to receive internal control signal(s) and first and second input signals and to output a result signal. The CL is capable of outputting the result signal resulting from a logic function that is responsive to the internal control signal(s) and a signal of a group of signals including the first and second input signals. The CL is configured to receive the first input signal via the node in the PCM tile.

Claims20

Dependent claims

A programmable device comprising:

a first die comprising a programmable computational memory (PCM) integrated circuit, the PCM integrated circuit comprising a PCM tile, the PCM tile comprising:
a configuration memory capable of storing configuration data, the configuration memory being configured to receive the configuration data via a first node in the PCM tile;
and
first combinational logic configured to receive one or more first internal control signals, a first input signal, and a second input signal and to output on a first output node a first result signal, the one or more first internal control signals being based on the configuration data and one or more external control signals received by the PCM tile, the first combinational logic being capable of outputting the first result signal resulting from at least one of a plurality of logic functions that is responsive to the one or more first internal control signals and at least one signal of a group of signals including the first input signal and the second input signal, the first combinational logic being configured to receive the first input signal via the first node in the PCM tile.

1 more element

A programmable device comprising:

a first die comprising an interconnect circuit;
and
a second die comprising a first programmable computational memory (PCM) array, the second die being stacked on and communicatively coupled to the first die, the first PCM array comprising first PCM tiles, the first PCM tiles being interconnected to form at least a portion of a first signal transmission network, each of the first PCM tiles comprising a configuration memory, each of the first PCM tiles being configurable to operate in one of a plurality of functional modes based on configuration data stored in the configuration memory of the respective first PCM tile, the first die being operable to transmit configuration data to one or more of the first PCM tiles via the first signal transmission network, when one or more of the first PCM tiles operate in respective functional modes, the one or more of the first PCM tiles are configured to communicate via the first signal transmission network.

Dependencies are inferred from the claim text.

Facts

Application: 16/539,220Filed 13 Aug 2019
Granted: 2 Jun 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H03K 19/1776
Structural details of configuration resources: for memories
G06F 3/067
Adopting a particular infrastructure: distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
G06F 7/483
Using non-contact-making devices, e.g. tube, solid state device; using unspecified devices: computations with numbers represented by a non-linear…
H03K 19/17724
Arranged in matrix form: structural details of logic blocks