Scrubbing controllers of semiconductor memory devices, semiconductor memory devices and methods of operating the same

A semiconductor memory device, comprising:

• a memory cell array including a plurality of bank arrays;
• a control logic circuit configured to control access to the memory cell array in response to a command and an address from an external memory controller;
• a plurality of error correction code (ECC) engines corresponding to the plurality of bank arrays;
• and
• a scrubbing controller including a plurality of scrubbing control engines corresponding to the plurality of bank arrays, respectively,
• wherein the control logic circuit is configured to, in response to a scrubbing command provided from the memory controller, control the ECC engines and the scrubbing control engines such that a normal scrubbing operation is sequentially performed on all codewords in a first bank array of the plurality of bank arrays and a weak scrubbing operation is sequentially performed on weak codewords of a second bank array of the plurality of bank arrays except the first bank array, and
• wherein the normal scrubbing operation and the weak scrubbing operation are performed at the same time.

A scrubbing controller of a semiconductor memory device, the scrubbing controller comprising:

• a scrubbing address generator configured to perform a normal scrubbing operation by generating a scrubbing address for a plurality of codewords in a first bank array of a plurality of bank arrays;
• and
• a weak codeword address generator configured to perform a weak scrubbing operating by generating a weak codeword address for a plurality of weak codewords in a second bank array of the plurality of bank arrays,
• wherein the normal scrubbing operation is performed on the codewords in the first bank array while the weak scrubbing operation is performed on the weak codewords in the second bank array.