Dual voltage controlled oscillator circuits for a broadband phase locked loop for multi-band millimeter-wave 5G communication

A dual voltage controlled oscillator (VCO) circuit, the circuit comprising:

• a first VCO circuit to generate a first signal having a first frequency in a first frequency band, the first VCO circuit including:
• a first variable capacitor having an input node, a first output node, and a second output node;
• a second variable capacitor connected in parallel with the first variable capacitor;
• a first transistor having a first drain terminal, a first gate terminal, and a first source terminal, wherein the first drain terminal is coupled to the first output node, the first gate terminal is coupled to the second output node, and the first source terminal is coupled to a ground node;
• and
• a second transistor having a second drain terminal, a second gate terminal, and a second source terminal, wherein the second drain terminal is coupled to the second output node and the second gate terminal is coupled to the first output node, and the second source terminal is coupled to the ground node;
• a second VCO circuit to generate a second signal having a second frequency in a second frequency band greater than the first frequency band, the second VCO circuit including:
• a third variable capacitor having the input node, a third output node, and a fourth output node;
• a fourth variable capacitor connected in parallel with the third variable capacitor;
• a third transistor having a third drain terminal, a third gate terminal, and a third source terminal, wherein the third drain terminal is coupled to the third output node, the third gate terminal is coupled to the fourth output node, and the third source terminal is coupled to the ground node;
• and
• a fourth transistor having a fourth drain terminal, a fourth gate terminal, and a fourth source terminal, wherein the fourth drain terminal is coupled to the fourth output node, the fourth gate terminal is coupled to the third output node, and the fourth source terminal is coupled to the ground node;
• a first inductor coupled in between the first output node and the second output node to resonate with the first and the second variable capacitors at the first frequency;
• a second inductor coupled in between the third output node and the fourth output node to resonate with the third and the fourth variable capacitors at the second frequency;
• a first buffer output network circuit coupled in between the first output node and the second output node;
• and
• a second buffer output network circuit coupled in between the third output node and fourth second output node.

A dual voltage controlled oscillator (VCO) circuit, the circuit comprising:

• a first VCO circuit to generate a first signal having a first frequency in a first frequency band, the first VCO circuit including:
• a first variable capacitor having an input node, a first output node, and a second output node;
• a second variable capacitor connected in parallel with the first variable capacitor;
• a first transistor having a first drain terminal, a first gate terminal, and a first source terminal, wherein the first drain terminal is coupled to the first output node, the first gate terminal is coupled to the second output node, and the first source terminal is coupled to a ground node;
• and
• a second transistor having a second drain terminal, a second gate terminal, and a second source terminal, wherein the second drain terminal is coupled to the second output node and the second gate terminal is coupled to the first output node, and the second source terminal is coupled to the ground node;
• a second VCO circuit to generate a second signal having a second frequency in a second frequency band greater than the first frequency band, the second VCO circuit including:
• a third variable capacitor having the input node, a third output node, and a fourth output node;
• a fourth variable capacitor connected in parallel with the third variable capacitor;
• a third transistor having a third drain terminal, a third gate terminal, and a third source terminal, wherein the third drain terminal is coupled to the third output node, the third gate terminal is coupled to the fourth output node, and the third source terminal is coupled to the ground node;
• and
• a fourth transistor having a fourth drain terminal, a fourth gate terminal, and a fourth source terminal, wherein the fourth drain terminal is coupled to the fourth output node, the fourth gate terminal is coupled to the third output node, and the fourth source terminal is coupled to the ground node;
• a first inductor coupled in between the first output node and the second output node to resonate with the first and the second variable capacitors at the first frequency;
• and
• a second inductor coupled in between the third output node and the fourth output node to resonate with the third and the fourth variable capacitors at the second frequency,
• wherein the first, second, third, and fourth transistors include transistors with a larger gate length than other transistors of a phase locked loop circuit comprising the dual VCO circuit.

A phase locked loop circuit, the circuit comprising:

• a dual voltage controlled oscillator (VCO) circuit, the circuit comprising
• a first VCO circuit to generate a first signal having a first frequency in a first frequency band, the first VCO circuit including:
• a first variable capacitor having a first output node and a second output node;
• a second variable capacitor coupled in parallel with the first variable capacitor;
• a first transistor having a first drain terminal, a first gate terminal, and a first source terminal, wherein the first drain terminal is coupled to the first output node, the first gate terminal is coupled to the second output node, and the first source terminal is coupled to a ground node;
• and
• a second transistor having a second drain terminal, a second gate terminal, and a second source terminal, wherein the second drain terminal is coupled to the second output node and the second gate terminal is coupled to the first output node, and the second source terminal is coupled to the ground node;
• a second VCO circuit to generate a second signal having a second frequency in a second frequency band, the second VCO circuit including:
• a third variable capacitor having a third output node and a fourth output node;
• a fourth variable capacitor coupled in parallel with the third variable capacitor;
• a third transistor having a third drain terminal, a third gate terminal, and a third source terminal, wherein the third drain terminal is coupled to the third output node, the third gate terminal is coupled to the fourth output node, and the third source terminal is coupled to the ground node;
• and
• a fourth transistor having a fourth drain terminal, a fourth gate terminal, and a fourth source terminal, wherein the fourth drain terminal is coupled to the fourth output node, the fourth gate terminal is coupled to the third output node, and the fourth source terminal is coupled to the ground node;
• a first inductor coupled in between the first output node and the second output node to resonate with the first and the second variable capacitors at the first frequency;
• and
• a second inductor coupled in between the third output node and the fourth output node to resonate with the third and the fourth variable capacitors at the second frequency;
• a multiplexer coupled to the first VCO circuit, the second VCO circuit, and a feedback loop;
• a control logic to select either the first VCO circuit or the second VCO circuit using the multiplexer to feed back a signal associated with the first VCO circuit or the second VCO circuit using the feedback loop;
• and
• a phase frequency detector coupled to the first VCO circuit and the second VCO circuit and the feedback loop, wherein the phase frequency detector is configured to receive a reference signal and the feedback signal to correct a frequency drift of the first or the second generated signal using the reference signal and the feedback signal.

A radio frequency (RF) frontend circuit comprising a phase locked loop circuit to generate a LO signal, the phase locked loop circuit comprising:

• a dual voltage controlled oscillator (VCO) circuit, the circuit comprising
• a first VCO circuit to generate a first signal having a first frequency in a first frequency band, the first VCO circuit including:
• a first variable capacitor having a first output node and a second output node;
• a second variable capacitor coupled in parallel with the first variable capacitor;
• a first transistor having a first drain terminal, a first gate terminal, and a first source terminal, wherein the first drain terminal is coupled to the first output node, the first gate terminal is coupled to the second output node, and the first source terminal is coupled to a ground node;
• and
• a second transistor having a second drain terminal, a second gate terminal, and a second source terminal, wherein the second drain terminal is coupled to the second output node and the second gate terminal is coupled to the first output node, and the second source terminal is coupled to the ground node;
• a second VCO circuit to generate a second signal having a second frequency in a second frequency band, the second VCO circuit including:
• a third variable capacitor having a third output node and a fourth output node;
• a fourth variable capacitor coupled in parallel with the third variable capacitor;
• a third transistor having a third drain terminal, a third gate terminal, and a third source terminal, wherein the third drain terminal is coupled to the third output node, the third gate terminal is coupled to the fourth output node, and the third source terminal is coupled to the ground node;
• and
• a fourth transistor having a fourth drain terminal, a fourth gate terminal, and a fourth source terminal, wherein the fourth drain terminal is coupled to the fourth output node, the fourth gate terminal is coupled to the third output node, and the fourth source terminal is coupled to the ground node;
• a first inductor coupled in between the first output node and the second output node to resonate with the first and the second variable capacitors at the first frequency;
• and
• a second inductor coupled in between the third output node and the fourth output node to resonate with the third and the fourth variable capacitors at the second frequency;
• a multiplexer coupled to the first VCO circuit, the second VCO circuit, and a feedback loop;
• a control logic to select either the first VCO circuit or the second VCO circuit using the multiplexer to feed back a signal associated with the first VCO circuit or the second VCO circuit using the feedback loop;
• and
• a phase frequency detector coupled to the first VCO circuit and the second VCO circuit and the feedback loop, wherein the phase frequency detector is configured to receive a reference signal and the feedback signal to correct a frequency drift of the first or the second generated signal using the reference signal and the feedback signal.