Schottky-CMOS asynchronous logic cells
AssigneeSchottky Lsi, Inc.
InventorsAugustine Wei-Chun Chang, Pierre Dermy
Life of this patent
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Abstract
Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.
Claims18
An integrated circuit implementing a NAND gate system, the integrated circuit comprising:
- a first input coupled to a cathode of a first Schottky diode;
- x additional inputs coupled to x respective cathodes of x additional Schottky diodes, wherein x is an integer number;
- an inverter having an inverter input and an inverter output, wherein:
- the integrated circuit is configured for asynchronous operation;
- the inverter is biased between a high voltage supply and a low voltage supply;
- the inverter input is coupled to an anode of the first Schottky diode and x respective anodes of the x additional Schottky diodes;
- and
- the inverter output is coupled to an output of the NAND gate system;
- and
- a source follower tree including one or more N-type transistors, wherein the source follower tree is biased between the high voltage supply and the inverter input.
An integrated circuit implementing a NOR gate system, the integrated circuit comprising:
- a first input coupled to an anode of a first Schottky diode;
- x additional inputs coupled to x respective anodes of x additional Schottky diodes, wherein x is an integer number;
- an inverter having an inverter input and an inverter output, wherein:
- the integrated circuit is configured for asynchronous operation;
- the inverter is biased between a high voltage supply and a low voltage supply;
- the inverter input is coupled to a cathode of the first Schottky diode and x respective cathodes of the x additional Schottky diodes;
- and
- the inverter output is coupled to an output of the NOR gate system;
- and
- a source follower tree including one or more P-type transistors, wherein the source follower tree is biased between the inverter input and the low voltage supply.
Dependencies are inferred from the claim text.