Memory-based distributed processor architecture

A distributed processor on a memory chip, comprising:

• a substrate;
• a memory array disposed on the substrate, the memory array including a plurality of discrete memory banks;
• and
• a processing array disposed on the substrate, the processing array including a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks;
• and
• a plurality of buses, each one of the plurality of buses connecting one of the plurality of processor subunits to a corresponding, dedicated one of the plurality of discrete memory banks,
• wherein the plurality of buses are free of timing hardware logic components such that data transfers between a processor subunit and a corresponding, dedicated one of the plurality of discrete memory banks and across a corresponding one of the plurality of buses are uncontrolled by timing hardware logic components.

A distributed processor, comprising:

• a substrate;
• a memory array disposed on the substrate, the memory array including a plurality of discrete memory banks;
• and
• a processing array disposed on the substrate, the processing array including a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks;
• and
• a plurality of buses, each one of the plurality of buses connecting one of the plurality of processor subunits to at least another one of the plurality of processor subunits,
• wherein the plurality of processor subunits are configured to execute software that controls timing of data transfers across the plurality of buses to avoid colliding data transfers on at least one of the plurality of buses.