Memory systems including support for transposition operations and related methods and circuits
AssigneeUniversity of Virginia Patent Foundation
InventorsMohamed Ezzat El Hadedy Aly, Kevin Skadron
Life of this patent
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Abstract
A method operating a memory system, can be provided by reading a plurality of data words from a memory system, where each of the plurality of data words is stored in the memory system in a first dimension-major order. The plurality of data words can be shifted into a transpose memory system in the first dimension in parallel with one another using first directly time adjacent clock edges to store a plurality of transposed data words in a second dimension-major order in the transpose memory system relative to the memory system. The plurality of transposed data words can be shifted out of the transpose memory system in the second dimension using second directly time adjacent clock edges.
Claims16
A method operating a memory system, the method comprising:
- reading a plurality of data words from a memory system, wherein each of the plurality of data words is stored in the memory system in a first dimension-major order;
- shifting the plurality of data words into a transpose memory system in the first dimension using first directly time adjacent clock edges to store a plurality of transposed data words in a second dimensions-major order in the transpose memory system relative to the memory system;
- shuffling at least one of the plurality of transposed data words in the first dimension-major order and/or in the second dimension-major order in the memory system responsive to a code word that identifies a shift register cell in the in the memory system to which the at least one of the plurality of transposed data words is to be shuffled to provide a plurality of shuffled transposed data words;
- and
- shifting the plurality of shuffled transposed data words out of the transpose memory system in the second dimension using second directly time adjacent clock edges, wherein the transpose memory system comprises a plurality of memory cells each including a respective first pair of sequential logic circuits with respective inputs both connected to first adjacent ones of the plurality of memory cells in the first and second dimensions and each including respective outputs both connected to second adjacent ones of the plurality of memory cells in the first and second dimensions, wherein each of the plurality of memory cells further includes a respective second pair of sequential logic circuits with respective inputs both connected to the second adjacent ones of the plurality of memory cells in the first and second dimensions and each including respective outputs both connected to the respective inputs of the respective first pair of sequential logic circuits.
A transpose memory system comprising:
- a plurality of memory cells arranged in an array of rows and columns, the plurality of memory cells coupled together to provide a plurality of shift registers, wherein the shift registers are configured to shift data provided to the transpose memory system in a row direction of the array or in a column direction of the array responsive to a control signal to the plurality of memory cells using directly time adjacent clock edges to provide a plurality of transposed data words from the transpose memory system, wherein a first one of the plurality of memory cells comprises a first register and a second register each including a respective first pair of sequential logic circuits with respective inputs both connected to first adjacent ones of the plurality of memory cells in the row and column directions and each including respective outputs both connected to second adjacent ones of the plurality of memory cells in the row and column directions, wherein each of the plurality of memory cells further includes a respective second pair of sequential logic circuits with respective inputs both connected to the second adjacent ones of the plurality of memory cells in the row and column directions and each including respective outputs both connected to the respective inputs of the respective first pair of sequential logic circuits, wherein the first register provides storage for data moved from the first one of the plurality of memory cells to a second one of the plurality of memory cells and wherein the second register provides storage for data moved from the second one of the plurality of memory cells to the first one of the plurality of memory cells to provide shuffling of transposed data in the transpose memory system.
Dependencies are inferred from the claim text.