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US 10,664,001 B2Granted
RF square-law circuit
AssigneeQUALCOMM Incorporated
InventorsMohamed Abouzied, Rajagopalan Rangarajan, Peter Shah
Life of this patent
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Abstract
A circuit includes a first transistor that conducts a first current responsive to a DC bias voltage and an RF signal. A second transistor conducts a second current responsive to the DC bias voltage. The first current and the second current are mirrored through a pair of current mirrors coupled together through a low-pass filter to filter the envelope of the RF signal.
Claims20
A square-law circuit comprising:
- a first transistor having a gate coupled to a bias voltage and RF signal node for a bias voltage and an RF signal, the first transistor configured to conduct a first current responsive to the bias voltage and to the RF signal;
- a first current mirror configured to mirror the first current into an output current conducted by a first current mirror transistor;
- a second transistor having a gate coupled to a bias voltage node for the bias voltage, the second transistor configured to conduct a second current responsive to the bias voltage;
- a second current mirror configured to mirror the second current into a reference current conducted by a second current mirror transistor;
- and
- a low-pass filter including a filter capacitor coupled between a gate of the first current mirror transistor and a gate of the second current mirror transistor.
3 more elements
A method of detecting an envelope for an RF signal, comprising:
- driving a gate of a first transistor with a direct current (DC) bias voltage and the RF signal to conduct a first current through the first transistor, the first current including a rectified current responsive to the RF signal;
- biasing a gate of a second transistor with the DC bias voltage to conduct a second current through the second transistor;
- mirroring the second current through a first current mirror including a first current mirror transistor to conduct a reference current through the first current mirror transistor;
- and
- mirroring the first current through a second current mirror including a second current mirror transistor to conduct an output current through the second current mirror transistor, wherein mirroring the first current through the second current mirror includes filtering the first current through a low-pass filter having a filter capacitor coupled between a gate of the first current mirror transistor and a gate of the second current mirror transistor so that the output current includes an envelope current equaling a low-pass filtered version of the rectified current.
2 more elements
A square-law circuit, comprising:
- a first current mirror configured to mirror a combination of a rectified input current responsive to an RF input signal and a bias current into an output current, the first current mirror including a first current mirror transistor;
- a second current mirror configured to mirror the bias current into a reference current, the second current mirror including a second current mirror transistor;
- and
- a low-pass filter including a filter capacitor coupled between a gate of the first current mirror transistor and a gate of the second current mirror transistor.
1 more element
Dependencies are inferred from the claim text.