Semiconductor device
AssigneeRenesas Electronics Corporation
InventorMasataka Minami
Life of this patent
Estimating the term…
Abstract
A semiconductor device that can perform voltage monitoring with a small circuit area is provided. The resistive subdivision circuit RDIV performs the resistive subdivision of the input voltage Vin by means of the input ladder resistor (R1-R4), and drives the nMOS transistors MN1-MN3 by the subdivided input voltages Vi1-Vi3 each having different resistive subdivision ratios, respectively. The pMOS transistor MP0 is provided in common for the pMOS transistors MP1-MP3, and configures a current mirror circuit with each of the pMOS transistors MP1-MP3. The bias current generating circuit IBSG supplies a bias current to the pMOS transistor MP1.
Claims12
A semiconductor device comprising:
- a resistive subdivision circuit generating a first comparison voltage and a second comparison voltage different from the first comparison voltage based on subdividing an input voltage with different resistive subdivision ratios;
- a first voltage detection circuit outputting a result of a comparison between a reference voltage and the first comparison voltage to an output node of the first voltage detection circuit;
- a second voltage detection circuit outputting a result of a comparison between the reference voltage and the second comparison voltage to an output node of the second voltage detection circuit;
- wherein the first voltage detection circuit includes:
- a first transistor of a first conductive type coupled between the output node and a first power supply;
- and
- a first transistor of a second conductive type having a gate supplied with the first comparison voltage, and coupled between the output node and a second power supply,
- wherein the second voltage detection circuit includes:
- a second transistor of the first conductive type coupled between the output node and the first power supply;
- and
- a second transistor of the second conductive type having a gate supplied with the second comparison voltage, and coupled between the output node and the second power supply,
- wherein a mirror current flows through each of the first and second transistors of the first conductivity type, the mirror current caused by a third transistor of the first conductivity type having a gate and a drain commonly coupled to a gate of the first transistor of the first conductivity type and a gate of the second transistor of the first conductivity type, and
- wherein the third transistor is supplied with a bias current by a bias current generating circuit.
Dependencies are inferred from the claim text.