PLC, network unit, CPU, and data transfer method
AssigneeMitsubishi Electric Corporation
InventorKatsuhiro Annen
Life of this patent
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Abstract
A received-data writer of a network unit records first data in a first data area when a flag is set indicating that a write is allowed, and records second data in a second data area. The first data are data for which data consistency is to be guaranteed among received data that is received from the first slave station and a second slave station, and the second data are data for which real-timeliness is to be guaranteed among the received data. A first transferrer of a CPU transfers the first data recorded in the first data area to a first storage at an interval of a first transfer period when the flag is set indicating that a read is allowed. A second transferrer of the CPU transfers the second data recorded in the second data area to a second storage at an interval of a second transfer period.
Claims10
A programmable logic controller (PLC) comprising a central processing unit (CPU), network circuitry, and a shared memory readable and writable by the CPU and the network circuitry, wherein
- the shared memory includes a first data area and a second data area,
- the network circuitry includes
- a received-data writer to (i) record first data in the first data area when a flag is set indicating that a write to the first data area is allowed, the first data being data for which data consistency is to be guaranteed among received data that is received from a device connected via a network, and (ii) record second data in the second data area, the second data being data for which real-timeliness is to be guaranteed among the received data, and
- the CPU includes
- a storage,
- a first transferrer to read the first data from the first data area and transfer the first data to the storage at an interval of a first transfer period when the flag is set indicating that a read from the first data area is allowed, and
- a second transferrer to read the second data from the second data area and transfer the second data to the storage at an interval of a second transfer period that is different from the first transfer period.
Network circuitry configured to send and receive data via a shared memory to and from a central processing unit (CPU), the network circuitry and the CPU being included in a programmable logic controller (PLC), wherein
- the shared memory includes a first data area to store first data for which data consistency is to be guaranteed and a second data area to store second data for which real-timeliness is to be guaranteed, the first data being transferrable to the CPU at an interval of a first transfer period, the second data being transferrable to the CPU at an interval of a second transfer period,
- the network circuitry records the first data in the first data area when a flag is set indicating that a write to the first data area is allowed, the first data being data for which data consistency is to be guaranteed among data received from a device connected via a network, and
- the network circuitry records, in the second data area, the second data for which real-timeliness is to be guaranteed among the data received from the device.
A central processing unit (CPU) configured to send and receive data via a shared memory to and from network circuitry, the network circuitry and the CPU being included in a programmable logic controller (PLC), the CPU comprising:
- a storage;
- a first transferrer to read first data from the shared memory and transfer the first data to the storage at an interval of a first transfer period when a flag is set indicating that a read from the shared memory is allowed, the first data being data for which data consistency is to be guaranteed among data stored in the shared memory;
- and
- a second transferrer to read second data from the shared memory and transfer the second data to the storage at an interval of a second transfer period that is different from the first transfer period, the second data being data for which real-timeliness is to be guaranteed among the data stored in the shared memory.
A data transfer method for transferring data between a central processing unit (CPU) and network circuitry via a shared memory readable and writable by the CPU and the network circuitry, the CPU and the network circuitry being included in a programmable logic controller (PLC), the data transfer method comprising:
- recording, by the network circuitry, first data in the shared memory when a flag is set indicating that a write to the shared memory is allowed, the first data being data for which data consistency is to be guaranteed among received data that is received from a device connected via a network,
- recording, by the network circuitry, second data in the shared memory, the second data being data for which real-timeliness is to be guaranteed among the received data,
- reading, by the CPU, the first data from the shared memory and transferring, by the CPU, the first data to a storage of the CPU at an interval of a first transfer period when the flag is set indicating that a read from the shared memory is allowed, and
- reading, by the CPU, the second data from the shared memory and transferring, by the CPU, the second data to the storage at an interval of a second transfer period that is different from the first transfer period.
Dependencies are inferred from the claim text.