Three dimensional integrated circuit electrostatic discharge protection and prevention test interface

A system to provide electrostatic discharge protection to a wafer comprising:

• a probe card assembly electrically connected to a plurality of input/output channels, the probe card assembly comprising:
• a probe card printed circuit board (PCB),
• a probe card substrate adjacent the probe card PCB,
• a probe card head adjacent the probe card substrate and opposite the PCB, and
• a plurality of probe card pins connected to the probe card head;
• and
• a secondary assembly comprising an interposer electrically coupled to one or more wafers, each wafer comprising at least a device under test,
• wherein when the probe card pins couple probe pads on the wafer, two voltages with a same magnitude but different signs are sequentially applied on at least one of the plurality of input/output channels to dissipate charges resident on the wafer to provide electrostatic discharge protection.

A probe card assembly comprising:

• a grounding printed circuit board (PCB) electrically connected to a plurality of input/output channels;
• a probe card substrate adjacent the grounding PCB;
• a probe card head adjacent the probe card substrate and opposite the grounding PCB;
• and
• a plurality of probe card pins connected to the probe card head,
• wherein the plurality of probe card pins are configured to couple a wafer comprising at least a device under test, and wherein when the plurality of probe card pins couple the wafer, voltage is forced on ones of the plurality of input/output channels to dissipate charges resident on the wafer to provide electrostatic discharge protection, and
• wherein the probe card substrate includes a conductive material and can mate with any type of probe card head.