Hybrid backward-compatible signal encoding and decoding

A computer processor hardware system comprising:

• parser logic to parse a data stream into first portions of encoded data and second portions of encoded data;
• a first decoder to decode the first portions of encoded data into a first rendition of a signal at a first resolution;
• a second decoder to decode the second portions of encoded data into reconstruction data, the reconstruction data comprising hierarchical residual data and the reconstruction data specifying how to modify the first rendition of the signal;
• and
• the second decoder applying the reconstruction data to the first rendition of the signal to produce a second rendition of the signal, the hierarchical residual data comprising portions of data that are applied at different resolution levels, the second rendition of the signal being a higher resolution than the first rendition of the signal.