Image processing apparatus and image processing method

An image processing method comprising:

• inputting a plurality of pixels composing an input image in raster scan order,
• performing a correction operation for correcting positions of the plurality of pixels based on distortion of the input image to calculate corrected pixels, by
• calculating corrected pixel positions which are positions of the pixels to be outputted by the correction operation, from input pixel positions which are positions of the inputted pixels,
• calculating, by an operation, pixel positions of the input image corresponding to the calculated corrected pixel positions and corresponding to pixel positions of a plurality of pixels in a periphery of the calculated corrected pixel positions,
• calculating the corrected pixels, which correspond to the calculated pixel positions of the input image,
• attaching information on the corrected pixel positions obtained as a result of the correction operation to calculate the corrected pixels,
• outputting the corrected pixels to which the information on the corrected pixel positions is attached;
• and
• writing a corrected pixel outputted in a random order based on the information on the corrected pixel positions in a first-stage output buffer of a plurality of output buffers layered to two or more stages, sequentially transferring the written corrected pixel to a post-stage output buffer to cause output buffers at respective stages to store pixels of sub-blocks which are a set of corrected pixels with consecutive corrected pixel positions, and outputting pixels of a transmission block in which a plurality of sub-blocks stored in the output buffers at respective stages are concatenated.

An image processing apparatus comprising:

• a distortion correction circuit to which a plurality of pixels composing an input image are inputted in raster scan order, and which is configured to perform a correction operation for correcting positions of the plurality of pixels based on distortion of the input image to calculate corrected pixels,
• a plurality of output buffers layered to two or more stages to which an output of the distortion correction circuit is inputted in a random order based on information on the corrected pixel positions, and which are configured to output corrected pixels for each transmission block which is a set of corrected pixels with consecutive corrected pixel positions;
• and
• a controller configured to write an output pixel of the distortion correction circuit in a first-stage output buffer of the plurality of output buffers, sequentially transfer the written pixel to a post-stage output buffer, and cause output buffers at respective stages to store pixels of sub-blocks into which each transmission block is divided,
• wherein the plurality of output buffers layered to two or more stages include a smaller number of output buffers at a later stage.

An image processing apparatus comprising:

• a distortion correction circuit to which a plurality of pixels composing an input image are inputted in raster scan order, and which is configured to perform a correction operation for correcting positions of the plurality of pixels based on distortion of the input image to calculate corrected pixels,
• a plurality of output buffers layered to two or more stages to which an output of the distortion correction circuit is inputted in a random order based on information on the corrected pixel positions, and which are configured to output corrected pixels for each transmission block which is a set of corrected pixels with consecutive corrected pixel positions;
• and
• a controller configured to write an output pixel of the distortion correction circuit in a first-stage output buffer of the plurality of output buffers, sequentially transfer the written output pixel to a post-stage output buffer, and cause output buffers at respective stages to store pixels of sub-blocks into which each transmission block is divided,
• wherein the controller gives tag information for specifying an image position for one of the sub-blocks written in the first-stage output buffer of the plurality of output buffers.