Scalable packet processing
AssigneeIntel Corporation
InventorsDan Christian Biederman, Matthew James Webb
Life of this patent
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Abstract
Particular embodiments described herein provide for an electronic device that includes at least one processor operating at eight hundred (800) megahertz and can be configured to receive a data stream, parse packets in the data stream, and process at least two (2) full packets from the data stream in a single clock cycle. In an example, the data stream is at least a two hundred (200) gigabit Ethernet data stream and a bus width is at least thirty-two (32) bytes.
Claims25
An electronic device comprising:
- memory;
- a processing engine;
- and
- at least one processor, operating at eight hundred (800) megahertz, wherein the processing engine is configured to cause the at least one processor to:
- receive a data stream, wherein the data stream is at least a two hundred (200) gigabit Ethernet data stream and a bus width is at least thirty-two (32) bytes;
- parse packets in the data stream and identify a start and an end of packets in the data stream;
- and
- process at least two (2) full packets from the data stream in a single clock cycle.
At least one non-transitory machine readable medium comprising one or more instructions that, when executed by at least one processor operating at eight hundred (800) megahertz, causes the at least one processor to:
- receive a data stream, wherein the data stream is at least a two hundred (200) gigabit data stream and a bus width is at least thirty-two (32) bytes;
- parse packets in the data stream and identify a start and an end of packets in the data stream;
- and
- process at least one (1) full packet and two (2) partial packets from the data stream in a single clock cycle.
A method comprising:
- receiving a data stream;
- parsing packets in the data stream and identifying a start and an end of packets in the data stream;
- and
- processing at least two (2) full packets from the data stream in a single clock cycle, wherein the packets are processed using a frame channel engine.
A system for scalable packet processing, the system comprising:
- memory;
- one or more processors operating at eight hundred (800) megahertz;
- and
- a processing engine, wherein the processing engine is configured to:
- receive a data stream;
- parse packets in the data stream and identify a start and an end of packets in the data stream;
- and
- process at least four (4) packets from the data stream in a single clock cycle.
Dependencies are inferred from the claim text.