Method and apparatus to provide both high speed and low speed signaling from the high speed transceivers on an field programmable gate array

A system for testing a device under test (DUT) that outputs a first low speed signal and a high speed signal, the system comprising:

• field programmable gate array (FPGA) comprising a high speed transceiver coupled to the first low speed signal;
• and a programmable logic block connected to the high speed transceiver, the programmable logic block comprising:
• a protocol logic block;
• a sampling logic block adapted to perform the following steps:
• a. receive a high speed transceiver sample pattern from the high speed transceiver based on the first low speed signal from the DUT;
• b. determine from the high speed transceiver sample pattern each frame of a plurality of frames;
• and
• c. for each frame, determine whether the high speed sample pattern encodes a zero or a one;
• and
• a bit replication logic block adapted to perform the following steps:
• a. receive an input bit pattern from the protocol logic block that comprises a plurality of bits;
• b. determine an appropriate bit replication multiplier:
• c. for each bit in the input bit pattern, create a bit replication pattern comprising a series of bits equal to the bit replication multiplier and based on a value of a respective bit in the input bit pattern;
• d. pass the bit replication pattern to the high speed transceiver;
• and
• a testing resource connected to the FPGA, wherein the testing resource is adapted to communicate with the DUT, wherein the high speed transceiver is adapted to receive a high speed signal from the DUT, wherein the programmable logic block bypasses the sampling logic block and passes the high speed signal to the protocol logic block.

A method of reading a low speed signal from a device under test (DUT) that outputs the low speed signal and a high speed signal, the low speed signal processed through a high speed transceiver, the method comprising:

• programming sampling logic coupled to the high speed transceiver to:
• a. receive a high speed sample pattern from the high speed transceiver based on the low speed signal;
• b. determine from the high speed sample pattern each frame of a plurality of frames;
• and
• c. for each frame, determine whether the high speed sample pattern encodes a zero or a one;
• programming bit replication logic also coupled to the high speed transceiver to:
• a. receive an input bit pattern that comprises a plurality of bits;
• b. determine an appropriate bit replication multiplier;
• c. for each bit in the input bit pattern, create a bit replication pattern comprising a series of bits equal to the bit replication multiplier and based on a value of a respective bit in the input bit pattern;
• d. pass the bit replication pattern to the high speed transceiver;
• and
• wherein the high speed transceiver is configured to receive the high speed signal, wherein the high speed signal is configured to bypass the sampling logic.