Logic circuit for codeword synchronization for fiber channel protocol

A logic circuit for performing codeword synchronization in a transmission over a network, wherein the logic circuit is configured to:

• identify a codeword boundary by detecting known patterns in a bit codeword in the transmission;
• sample bit data from a fiber channel (FC) link, wherein the bit data is used to detect the known patterns for all candidate positions in the bit codeword;
• find known patterns on one candidate position sequentially, wherein when the known patterns on one candidate position sequentially are found, the codeword boundary is identified;
• and
• output a position offset to achieve transmission synchronization when the codeword boundary is identified.

A logic circuit for performing codeword synchronization in a transmission over a network, wherein the logic circuit is configured to:

• detect dedicated bit patterns for bit data in each transmission word of a codeword to determine a boundary of the codeword;
• and
• detect a known pattern on candidate bits from input data candidate bits and recording the detected results of the candidate bits in a pattern found counter,
• wherein when a bit pattern is found for the codeword, a next codeword cycle starts and a codeword slip bit in the bit data input is calculated.