Overclocked line rate for communication with PHY Interfaces
AssigneeAvago Technologies International Sales Pte. Limited
InventorsVelu Pillai, Vivek Telang
Life of this patent
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Abstract
A system side interface of a PHY chip used in conjunction with a 100 GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.
Claims20
A switch controller including:
- switch circuitry coupled to a backplane via first PHY circuitry, the first PHY circuitry configured to communicate with the switch circuitry via a first signaling protocol at an overclocked signaling rate, the overclocked signaling rate matching a signaling rate associated with a backplane signaling protocol;
- control circuitry coupled to the backplane via second PHY circuitry, the second PHY circuitry configured to communicate with the control circuitry via the first signaling protocol, and at the overclocked signaling rate;
- and
- a backplane coupling the first PHY circuitry to the second PHY circuitry, the backplane configured to communicate with the first PHY circuitry and the second PHY circuitry using the backplane signaling protocol at the signaling rate associated with the backplane signaling protocol.
A data processing system including:
- a first processing device coupled to a first PHY chip, the first PHY chip coupled to a backplane, and configured to communicate with the first processing device via a first signaling protocol at an overclocked signaling rate, the overclocked signaling rate matching a signaling rate associated with a backplane signaling protocol;
- second processing device coupled to the backplane via a second PHY chip, the second PHY chip configured to communicate with the second processing device via the first signaling protocol, and at the overclocked signaling rate;
- and
- a backplane coupling the first PHY chip to the second PHY chip, the backplane configured to communicate with the first PHY chip and the second PHY chip using the backplane signaling protocol, and at the signaling rate associated with the backplane signaling protocol.
A data processing system including:
- a first PHY chip coupling to a first processing device to a physical communications medium, the first PHY chip configured to communicate with the first processing device via a first signaling protocol at an overclocked signaling rate, the overclocked signaling rate matching a signaling rate associated with a second signaling protocol used by the physical communications medium;
- and
- a second PHY chip coupling a second processing device to the physical communications medium, the second PHY chip configured to communicate with the second processing device via the first signaling protocol, and at the overclocked signaling rate.
Dependencies are inferred from the claim text.