Reconfigurable FEC
AssigneeInphi Corporation
InventorVolodymyr Shvydun
Life of this patent
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Abstract
The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.
Claims20
A forward-error correction (FEC) device with multiple operating modes for processing data from at least a first communication lane and a second communication lane operating at n-bit, n being associated with a data width, the FEC device comprising:
- a syndrome computation (SC) module configured to perform syndrome computation (SC) using a first processing module to generate an equation using a 2n-bit vector if the operating mode is in a 2n-bit mode, the 2n-bit vector including data from the first communication lane and the second communication lane, the 2n-bit vector being stored in a first vector module and a second vector module, the SC module further being configured to perform syndrome computation (SC) using a second processing module to generate the equation using a first n-bit vector if the operating mode is in a n-bit mode, the first n-bit vector including data from the first communication lane, the n-bit vector being stored in the first vector module;
- a key equation solver (KES) module coupled to the SC module and configured to generate a first polynomial and a second polynomial based at least on the equation;
- and
- a Chien Search (CS) being operational in multiple operating modes and configured to use at least the first polynomial to determine an error location.
A forward-error correction (FEC) device with multiple operating modes for processing data from at least a first communication lane and a second communication lane operating at n-bit, n being associated with a data width, the FEC device comprising:
- a syndrome computation (SC) module, the SC module comprising a plurality of processing modules, the plurality of processing modules including a first processing module and a second processing module, the first processing module being configured to operate in an n-bit mode and a 2n-bit mode for calculating syndrome polynomials for at least a first equation, the first processing module performing syndrome calculation using an n-bit vector based on data received from the first communication lane when operating in the n-bit mode, the first processing module performing syndrome calculation using a 2n-bit vector based on data received from the first communication lane and the second communication lane when operating in the 2n-bit mode,
- a key equation solver (KES) module coupled to the SC module, the KES module being configured to generate at least a first polynomial and a second polynomial based using at least the first equation;
- a Chien search (CS) module coupled to the KES module, the CS module comprising a plurality of sections, the plurality of sections including a first section and a second section, the first section being configured to operate in the n-bit mode and the 2n-bit mode for determining errors;
- and
- a first-in-first-out (FIFO) buffer.
A method for data communication, the method comprising:
- receiving data from a plurality of communication lanes, the plurality of communication lanes including a first communication lane and a second communication lane, the first communication lane and the second communication lane operating at n-bit, n being associated with a data width;
- aligning the data using at least an accumulator;
- storing the data at a buffer;
- determining an operating mode associated with the data;
- performing syndrome computation (SC) to generate an equation using a 4n-bit vector if the operating mode is in a 4n-bit mode, the 4n-bit vector including data at least from the first communication lane and the second communication lane, the SC computation being performed by a second processing module;
- performing syndrome computation (SC) using a first processing module to generate the equation using a first n-bit vector if the operating mode is in an n-bit mode, the first n-bit vector including data from the first communication lane, the n-bit vector being stored in the first vector module;
- solving the equation using a key equation solver (KES) module;
- generating a first polynomial and a second polynomial based at least on the equation;
- and
- performing a Chien Search (CS) using at least the first polynomial to determine an error location.
Dependencies are inferred from the claim text.