Signed-RFDAC architectures enabling wideband and efficient 5G transmitters

A radio frequency digital-to-analog converter (RFDAC) circuit comprising:

• an RFDAC array circuit comprising an array of cells arranged into a plurality of columns, each column comprising a set of cells, wherein each column of the plurality of columns is configured to process input data signals, and wherein the RFDAC array circuit is configured to:
• process an input data based on activating one or more columns of the plurality of columns, in accordance with a predefined first filling order, when the sign of the input data is positive;
• and
• process the input data based on activating one or more columns of the plurality of columns, in accordance with a predefined second, different, filling order, when the sign of the input data is negative;
• wherein the filling order comprises a predefined order in which the plurality of columns is configured to be activated, in order to process the input data.

A differential radio frequency digital-to-analog converter (RFDAC) circuit comprising:

• a differential RFDAC array circuit comprising an array of differential cells, each differential cell comprising a first half cell circuit and a second half cell circuit, wherein the first half cell circuit and the second half cell circuit are driven by a local oscillator (LO) signal and an inverse LO signal respectively, and wherein the differential RFDAC array circuit is configured to:
• process an input data based on activating the first half cell circuit and the second half cell circuit associated with a group of differential cells of the array of differential cells, simultaneously in each LO period, during regular operation;
• activate a first set of half cell circuits comprising either a set of first half cell circuits or a set of second half cell circuits in an LO period preceding a sign change associated with the input data, in order to process the input data during a sign change;
• and
• activate a second, different set of half cell circuits comprising either the set of first half cell circuits or the set of second half cell circuits that was not activated during the LO period preceding the sign change, in an LO period succeeding the sign change associated with the input data, in order to process the input data during the sign change.